公开(公告)号：US6011285A

公开(公告)日：2000-01-04

申请号：US2364

申请日：1998-01-02

申请人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien Hsiung Peng

发明人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien Hsiung Peng

IPC分类号： H01L21/8247 ,  C23C16/40 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L28/55 ,  C23C16/40 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/516 ,  H01L29/78391

摘要： The structure of a c-axis FEM cell semiconductor includes a silicon substrate; a source junction region and a drain junction region located in the substrate; a gate junction region located between the source junction region and the drain junction region; a FEM gate unit including a lower electrode, a c-axis oriented Pb.sub.5 Ge.sub.3 O.sub.11 FE layer and an upper electrode; wherein the FEM gate unit is sized on the gate junction region such that any edge of said FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and source, drain and gate electrodes.

摘要翻译： c轴FEM单元半导体的结构包括硅衬底; 源极结区域和位于衬底中的漏极结区域; 位于源极结区域和漏极结区域之间的栅极结区域; 包括下电极，c轴取向Pb5Ge3O11FE层和上电极的FEM门单元; 其中所述FEM门单元的尺寸设置在所述栅极结区域上，使得所述FEM栅极单元的任何边缘距离源极结区域和漏极结区域的边缘为距离“D” 绝缘层，具有覆盖接合区域的上表面，FEM门单元和衬底; 以及源极，漏极和栅极。

公开(公告)号：US06242771B1

公开(公告)日：2001-06-05

申请号：US09291688

申请日：1999-04-13

申请人： Sheng Teng Hsu ,  Chien Hsiung Peng ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Chien Hsiung Peng ,  Jong Jan Lee

IPC分类号： H01L29788

CPC分类号： H01L28/55 ,  C23C16/40 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/516 ,  H01L29/78391

摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; treating the device area to form area for a source, gate and drain region; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb5Ge3O11 FE layer by Chemical vapor deposition (CVD), and depositing an upper electrode; and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell includes: a single-crystal silicon substrate including an active region having source, gate and drain regions therein; a FEM gate unit including a lower electrode, a c-axis oriented Pb5Ge3O11 FE layer formed by CVD and an upper electrode; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source, gate and drain electrode.

摘要翻译： 在单晶硅的衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括：形成用于FEM门单元的硅器件区域; 处理器件区域以形成源极，栅极和漏极区域; 在所述栅极结区域上沉积FEM栅极单元，包括沉积下电极，通过化学气相沉积（CVD）沉积c轴取向的Pb5Ge3O11FE层，以及沉积上电极; 以及围绕所述FEM门单元沉积绝缘结构。 铁电存储器（FEM）单元包括：单晶硅衬底，其包括其中具有源极，栅极和漏极区域的有源区; 包括下电极，由CVD形成的c轴取向Pb5Ge3O11FE层和上电极的有限元门单元; 绝缘层，具有覆盖接合区域的上表面，FEM门单元和衬底; 以及源极，栅极和漏极。