公开(公告)号：US6071782A

公开(公告)日：2000-06-06

申请号：US23383

申请日：1998-02-13

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L21/28052 ,  H01L29/6659

摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.

摘要翻译： 提供了在整个源极/漏极区域以均匀的速率形成硅化物的工艺。 两步退火方法允许形成在硅电极边缘上的硅化物的厚度与电极中心基本相同。 首先，低温退火开始跨越源/漏电极表面的盐析过程。 控制时间和温度，使得金属仅被部分消耗。 中断退火以去除过量的硅化金属，特别是覆盖与硅电极相邻的氧化物区域的未反应的金属。 然后，在较高温度的退火下完成硅化。 由于去除了多余的金属，所得到的硅化物层是均匀平坦的，从而允许晶体管被制造成具有浅结的区域和低的漏电流。 在本发明的一个实施例中，源极和漏极表面的晶体结构在金属沉积之前被消除，以降低退火温度并且增加对硅化工艺的精确控制。 还提供了具有根据上述方法制造的均匀厚的硅化物层的晶体管。

公开(公告)号：US6011285A

公开(公告)日：2000-01-04

申请号：US2364

申请日：1998-01-02

申请人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien Hsiung Peng

发明人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien Hsiung Peng

IPC分类号： H01L21/8247 ,  C23C16/40 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L28/55 ,  C23C16/40 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/516 ,  H01L29/78391

摘要： The structure of a c-axis FEM cell semiconductor includes a silicon substrate; a source junction region and a drain junction region located in the substrate; a gate junction region located between the source junction region and the drain junction region; a FEM gate unit including a lower electrode, a c-axis oriented Pb.sub.5 Ge.sub.3 O.sub.11 FE layer and an upper electrode; wherein the FEM gate unit is sized on the gate junction region such that any edge of said FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and source, drain and gate electrodes.

摘要翻译： c轴FEM单元半导体的结构包括硅衬底; 源极结区域和位于衬底中的漏极结区域; 位于源极结区域和漏极结区域之间的栅极结区域; 包括下电极，c轴取向Pb5Ge3O11FE层和上电极的FEM门单元; 其中所述FEM门单元的尺寸设置在所述栅极结区域上，使得所述FEM栅极单元的任何边缘距离源极结区域和漏极结区域的边缘为距离“D” 绝缘层，具有覆盖接合区域的上表面，FEM门单元和衬底; 以及源极，漏极和栅极。

公开(公告)号：US5989965A

公开(公告)日：1999-11-23

申请号：US23032

申请日：1998-02-13

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656

摘要： A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces. A transistor, with an overhang structure, fabricated by the above-mentioned procedure is also provided.

摘要翻译： 提供了形成临时突出结构以屏蔽栅电极附近的源/漏边缘与沉积硅化金属的方法。 源极/漏极区域上的硅化物的生长保持受控，而在源极/漏极边缘附近的栅电极侧壁上不存在硅化金属。 所得到的硅化物层不具有干扰源极/漏极结区域的边缘增长。 通过用具有不同蚀刻选择性的两个绝缘体覆盖栅电极来形成突出结构。 顶绝缘体被各向异性地蚀刻，使得仅覆盖覆盖栅电极垂直侧壁的顶绝缘体保留。 暴露的底部绝缘体被各向同性地蚀刻以在顶部绝缘体和源极/漏极区域表面之间形成间隙。 当沉积硅化金属时，间隙防止金属沉积在栅电极和源/漏区表面之间。 还提供了通过上述方法制造的具有突出结构的晶体管。

公开(公告)号：US6018171A

公开(公告)日：2000-01-25

申请号：US834499

申请日：1997-04-04

申请人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien-Hsiung Peng

发明人： Sheng Teng Hsu ,  Jong Jan Lee ,  Chien-Hsiung Peng

IPC分类号： G11C11/22 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/115 ,  H01L29/78 ,  H01L21/8242

CPC分类号： G11C11/22 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391 ,  G11C11/223 ,  Y10S438/957

摘要： A method of forming the FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as a source junction region, a gate junction region and a drain junction region. A FEM cell includes a FEM gate unit formed on the substrate. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on the FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. A shallow junction layer is formed between the FEM gate unit and the gate junction region, as another conductive channel, which extends into the drain junction region. The FEM gate unit is spaced apart from the source region and the drain region, as is the conductive channel between the FEM gate unit and the gate junction region. Formation of the various conductive channels may take place at various stages of the manufacture, depending on what other devices are built on the substrate, and depending on the efficiencies of the various orders of construction. The structure of the FEM cell semiconductor includes a substrate, which may be a bulk silicon substrate or an SOI-type substrate. Conductive channels of two types are located above the substrate.

摘要翻译： 形成FEM单元半导体结构的方法包括在硅衬底上形成用于铁电存储器（FEM）栅极单元的器件区域。 将合适的杂质注入器件区域以形成导电沟道，用作源极结区域，栅极结区域和漏极结区域。 FEM单元包括形成在基板上的FEM门单元。 在FEM栅极单元器件区域上的FEM栅极单元的源极连接区域和漏极结区域之间形成栅极结区域，该FEM栅极单元包括下部金属层，铁电（FE）层和上部金属 层。 在FEM栅极单元和栅极结区域之间形成浅接合层，作为延伸到漏极结区域的另一个导电沟道。 有限元门单元与源极区和漏极区间隔开，也就是FEM门单元和栅极结区之间的导电沟道。 各种导电通道的形成可以在制造的各个阶段进行，这取决于衬底上构建的其它器件，以及各种施工顺序的效率。 FEM单元半导体的结构包括可以是体硅基板或SOI型基板的基板。 两种类型的导电通道位于基板上方。

公开(公告)号：US5821169A

公开(公告)日：1998-10-13

申请号：US692379

申请日：1996-08-05

申请人： Tue Nguyen ,  Chien-Hsiung Peng ,  Bruce Dale Ulrich

发明人： Tue Nguyen ,  Chien-Hsiung Peng ,  Bruce Dale Ulrich

IPC分类号： H01L21/302 ,  G03F7/00 ,  H01L21/027 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/00 ,  B44C1/22

CPC分类号： H01L21/76811 ,  G03F7/00 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76813 ,  H01L2221/1021

摘要： A method is provided for forming intermediate levels in an integrated circuit dielectric during a damascene process using a hard mask layer to transfer the pattern of a photoresist mask having at least one intermediate thickness. The dielectric is covered with a hard mask layer, and the hard mask layer is covered with the photoresist mask. The photoresist mask pattern is transferred into the hard mask pattern so that the hard mask pattern has at least one intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the hard mask pattern. The hard mask pattern is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is etched to a second depth, less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The use of a relatively thin hard mask pattern reduces the degradation of vertical surface features, due to faceting, which generally occurs with the use of a thicker photoresist pattern. The method of the present invention allows a multi-level damascene process to be used to form features with relatively small geometries in the dielectric.

摘要翻译： 提供一种用于在镶嵌工艺期间在集成电路电介质中形成中间层的方法，其中使用硬掩模层来传递具有至少一个中间厚度的光致抗蚀剂掩模的图案。 电介质用硬掩模层覆盖，并且硬掩模层被光致抗蚀剂掩模覆盖。 将光致抗蚀剂掩模图案转印到硬掩模图案中，使得硬掩模图案具有至少一个中间厚度。 该方法通过硬掩模图案中的开口形成到电介质中的第一深度的互连。 硬掩模图案在中间厚度的区域中被部分地蚀刻掉以露出第二电介质表面积。 第二电介质表面积被蚀刻到比第一深度小的第二深度。 以这种方式，可以将通孔形成为第一深度，并且可以在第二深度处形成线以与通孔相交。 使用相对薄的硬掩模图案由于刻面而减少垂直表面特征的劣化，这通常通过使用较厚的光致抗蚀剂图案而发生。 本发明的方法允许使用多层镶嵌工艺来形成电介质中具有较小几何形状的特征。

公开(公告)号：US5629229A

公开(公告)日：1997-05-13

申请号：US501352

申请日：1995-07-12

申请人： Jie Si ,  Seshu B. Desu ,  Chien-Hsiung Peng

发明人： Jie Si ,  Seshu B. Desu ,  Chien-Hsiung Peng

IPC分类号： C30B29/22 ,  C23C16/40 ,  H01G4/12 ,  H01G4/33 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L28/55 ,  C23C16/40 ,  C23C16/409 ,  H01L21/31691 ,  H01L28/60

摘要： A dynamic random access memory device having a ferroelectric thin film perovskite (Ba.sub.1-x Sr.sub.x)TiO.sub.3 layer sandwiched by top and bottom (Ba.sub.1-x Sr.sub.x)RuO.sub.3 electrodes. The memory device is made by a MOCVD process including the steps of providing a semiconductor substrate, heating the substrate, exposing the substrate to precursors including at least Ru(C.sub.5 H.sub.5).sub.2, thereafter exposing the substrate to precursors including at least TiO(C.sub.2 H.sub.5).sub.4 and thereafter exposing the substrate to precursors including at least Ru(C.sub.5 H.sub.5).sub.2.

摘要翻译： 具有由顶部和底部（Ba1-xSrx）RuO3电极夹持的铁电薄膜钙钛矿（Ba1-xSrx）TiO3层的动态随机存取存储器件。 存储器件由MOCVD工艺制成，包括以下步骤：提供半导体衬底，加热衬底，将衬底暴露于至少包括Ru（C5H5）2）的前体，然后将衬底暴露于至少包含TiO（C 2 H 5）4 然后将基底暴露于至少包含Ru（C 5 H 5）2的前体。

公开(公告)号：US06339245B1

公开(公告)日：2002-01-15

申请号：US09378653

申请日：1999-08-20

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656

摘要： A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces. A transistor, with an overhang structure, fabricated by the above-mentioned procedure is also provided.

摘要翻译： 提供了形成临时突出结构以屏蔽栅电极附近的源/漏边缘与沉积硅化金属的方法。 源极/漏极区域上的硅化物的生长保持受控，而在源极/漏极边缘附近的栅电极侧壁上不存在硅化金属。 所得到的硅化物层不具有干扰源极/漏极结区域的边缘增长。 通过用具有不同蚀刻选择性的两个绝缘体覆盖栅电极来形成突出结构。 顶绝缘体被各向异性地蚀刻，使得仅覆盖覆盖栅电极垂直侧壁的顶绝缘体保留。 暴露的底部绝缘体被各向同性地蚀刻以在顶部绝缘体和源极/漏极区域表面之间形成间隙。 当沉积硅化金属时，间隙防止金属沉积在栅电极和源/漏区表面之间。 还提供了通过上述程序制造的具有突出结构的晶体管。

公开(公告)号：US06218249B1

公开(公告)日：2001-04-17

申请号：US09455588

申请日：1999-12-06

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L21336

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6659

摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.

摘要翻译： 提供了在整个源极/漏极区域以均匀的速率形成硅化物的工艺。 两步退火方法允许形成在硅电极边缘上的硅化物的厚度与电极中心基本相同。 首先，低温退火开始跨越源/漏电极表面的盐析过程。 控制时间和温度，使得金属仅被部分消耗。 中断退火以去除过量的硅化金属，特别是覆盖与硅电极相邻的氧化物区域的未反应的金属。 然后，在较高温度的退火下完成硅化。 由于去除了多余的金属，所得到的硅化物层是均匀平坦的，从而允许晶体管被制造成具有浅结的区域和低的漏电流。 在本发明的一个实施例中，源极和漏极表面的晶体结构在金属沉积之前被消除，以降低退火温度并且增加对硅化工艺的精确控制。 还提供了具有根据上述方法制造的均匀厚的硅化物层的晶体管。

公开(公告)号：US6043164A

公开(公告)日：2000-03-28

申请号：US665014

申请日：1996-06-10

申请人： Tue Nguyen ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Bruce Dale Ulrich ,  Chien-Hsiung Peng

发明人： Tue Nguyen ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Bruce Dale Ulrich ,  Chien-Hsiung Peng

IPC分类号： G03F7/36 ,  H01L21/027 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/0274 ,  H01L21/0334 ,  H01L2221/1021

摘要： A method is provided for forming an intermediate level in an integrated circuit dielectric during a damascene process using a photoresist mask having an intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the photoresist pattern. The photoresist profile is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is then etched to a second depth less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The method of the present invention allows a dual damascene process to be performed with a single step of photoresist formation.

摘要翻译： 提供一种用于在使用具有中间厚度的光致抗蚀剂掩模的镶嵌工艺期间在集成电路电介质中形成中间电平的方法。 该方法通过光致抗蚀剂图案中的开口形成到电介质中的第一深度的互连。 光致抗蚀剂轮廓在中间厚度的区域被部分地蚀刻掉以露出第二电介质表面积。 然后将第二电介质表面积蚀刻到小于第一深度的第二深度。 以这种方式，可以将通孔形成为第一深度，并且可以在第二深度处形成线以与通孔相交。 本发明的方法允许通过单步形成光致抗蚀剂来进行双镶嵌工艺。

公开(公告)号：US5593727A

公开(公告)日：1997-01-14

申请号：US148391

申请日：1993-11-08

申请人： Seshu B. Desu ,  Chien-Hsiung Peng ,  Tian Shi ,  Pradyot A. Agaskar

发明人： Seshu B. Desu ,  Chien-Hsiung Peng ,  Tian Shi ,  Pradyot A. Agaskar

IPC分类号： C01B33/00 ,  C08G77/12 ,  C23C16/00

CPC分类号： C08G77/12 ,  C01B33/00

摘要： The chemical vapor deposition of hydridospherosiloxane to generate films of SiO.sub.2 at low temperatures on substrates that cannot withstand high temperatures. The chemical vapor deposition process synthesized compounds with the general formula,(HSiO.sub.3/2).sub.n,with n being an even number ranging from 8 to a very large number. More particularly, it relates to the vapor deposition of oligomeric hydrogensilsesquioxanes, henceforth referred to as hydridospherosiloxanes. The hydridospherosiloxanes are used directly in a chemical vapor deposition reactor to generate films of SiO.sub.2 at low temperatures on substrates that cannot withstand high temperatures. Hydridospherosiloxanes and soluble hydrogensilsesquioxane resin are produced having the formula(HSiO.sub.3/2).sub.n,where n is an even integer greater than 8.

摘要翻译： 化学气相沉积氢化间苯二甲硅氧烷以在不能承受高温的基材上在低温下产生SiO 2膜。 化学气相沉积工艺合成具有通式（HSiO3 / 2）n的化合物，其中n为8至非常大的偶数。 更具体地说，本发明涉及低聚氢倍半硅氧烷的气相沉积，此后称为氢化间苯二甲硅氧烷。 氢化间苯二甲硅氧烷直接用于化学气相沉积反应器，以在低温下在不能承受高温的基材上产生SiO 2膜。 产生具有式（HSiO3 / 2）n的氢化间苯二酚硅烷和可溶性倍半硅氧烷树脂，其中n是大于8的偶数整数。