Blocks and bits sequence reversing device using barrel shift
    1.
    发明授权
    Blocks and bits sequence reversing device using barrel shift 失效
    块和位序列反转装置使用桶形移位

    公开(公告)号:US5265259A

    公开(公告)日:1993-11-23

    申请号:US547355

    申请日:1990-07-03

    CPC分类号: G06F7/78 G06F7/768

    摘要: A bit sequence reversing device for reversing a sequence of data having a plurality of blocks, each block having a predetermined number of bits. The bit sequence reversing device includes a block reversing unit for reversing a sequence of at least two of the blocks; and a plurality of bit reversing units, each corresponding to one of the blocks, each of the bit reversing units reversing a sequence of the bits in the corresponding block. The block reversing unit includes a barrel shift unit. The barrel shift unit includes first and second input latch circuits for receiving the data; a series of left shift registers, connected to the first input circuit, for shifting the output of the first input latch circuit on the left direction, a series of right shift registers, connected to the second input circuit, for shifting the output of the second input latch circuit on the right direction; a first output control circuit, connected to a post-stage of one of the left shift registers, for selectively outputting data thereof; and a second output control circuit, connected to a post-stage of one of the right shift registers, for selectively outputting data thereof. The bit sequence reversing device reduces execution time without increasing the structural elements thereof, and since the reversing operation of blocks is adjusted, various types of reversing operations are possible.

    Material for shadow mask, method for production thereof, shadow mask and image receiving tube
    2.
    发明授权
    Material for shadow mask, method for production thereof, shadow mask and image receiving tube 失效
    用于荫罩的材料,其制造方法,荫罩和图像接收管

    公开(公告)号:US06946041B2

    公开(公告)日:2005-09-20

    申请号:US10410306

    申请日:2003-04-10

    摘要: A material for shadow mask having the following composition of components: C≦0.0008 wt %, Si≦0.03 wt %, Mn:0.1 to 0.5 wt %, P≦0.02 wt %, S≦0.02 wt %, Al:0.01 to 0.07 wt %, N≦0.0030 wt %, B: an amount satisfying the formula: 5 ppm≦B−11/14×N≦30 ppm, balance: Fe and inevitable impurities; a method for producing the material; a shadow mask using the material (cold rolled steel sheet); and an image receiving tube equipped with the shadow mask. The material has excellent etching characteristics, which are uniform within the same coil, and excellent press formability.

    摘要翻译: 一种荫罩材料,其组成如下:C <0.0008重量%,Si <= 0.03重量%,Mn:0.1〜0.5重量%,P <0.02重量%,S <0.02重量%,Al: 0.01〜0.07重量%,N <0.0030重量%,B:满足下式的量:5ppm <= B-11/14×N <= 30ppm,余量:Fe和不可避免的杂质; 一种生产该材料的方法; 使用该材料(冷轧钢板)的荫罩; 以及配备有荫罩的图像接收管。 该材料具有优异的蚀刻特性,在相同的线圈内均匀,并且具有优异的压制成形性。

    Memory controller and a cache for accessing a main memory, and a system and a method for controlling the main memory
    3.
    发明授权
    Memory controller and a cache for accessing a main memory, and a system and a method for controlling the main memory 有权
    用于访问主存储器的存储器控​​制器和缓存,以及用于控制主存储器的系统和方法

    公开(公告)号:US06754778B2

    公开(公告)日:2004-06-22

    申请号:US10295855

    申请日:2002-11-18

    申请人: Taizo Sato

    发明人: Taizo Sato

    IPC分类号: G06F1200

    CPC分类号: G06F12/0804 G06F12/0215

    摘要: A memory control system has a replacement detection/notification circuit for detecting occurrence of replacement of dirty entry in a cache and informing a memory controller of the detection, and a state control circuit for precharging the currently active page in a main memory when the memory controller is informed of the detection and a preceding access to the main memory attendant upon the replacement of dirty entry is completed. By precharging the active page in the main memory to return to the idle state when the preceding access attendant upon the replacement of dirty entry is completed, the succeeding access can be done only by activating the aimed page probably different from the above page. It is thereby obviated to return the activated page due to the preceding access to the idle state after a page miss occurs in the succeeding access.

    摘要翻译: 存储器控制系统具有替换检测/通知电路,用于检测高速缓存中的脏条目的替换的发生以及通知存储器控制器的检测;以及状态控制电路,用于在存储器控制器中向主存储器预充电当前活动页面 被通知检测,并且在更换脏条目时完成对主存储器的先前访问。 通过在主存储器中预先充电活动页面以返回到空闲状态,当更换脏条目时前一访问服务器完成时,只有通过激活可能不同于上述页面的目标页面才能完成后续访问。 由于在后续访问中发生页错误之后,由于上述访问空闲状态而无法返回激活的页面。

    Information processing apparatus with parallel instruction decoding
    5.
    发明授权
    Information processing apparatus with parallel instruction decoding 失效
    具有并行指令解码的信息处理装置

    公开(公告)号:US5274792A

    公开(公告)日:1993-12-28

    申请号:US7032

    申请日:1993-01-21

    申请人: Taizo Sato

    发明人: Taizo Sato

    摘要: An information processing apparatus includes a decoder for decoding an instruction, a general purpose register part including a stack pointer and a plurality of general purpose registers, a special purpose register part including a plurality of special purpose registers, and a processing part coupled to the decoder, the general purpose register part and the special purpose register part for carrying out a predetermined process based on a decoded result from the decoder by selectively using a read out result of one of the general purpose register part and the special purpose register part. A decoding operation of the decoder, a read out operation of the general purpose register part and a read out operation of the special purpose register part are carried out in parallel.

    摘要翻译: 一种信息处理装置,包括用于解码指令的解码器,包括堆栈指针和多个通用寄存器的通用寄存器部分,包括多个专用寄存器的专用寄存器部分,以及耦合到解码器的处理部分 ,通用寄存器部分和专用寄存器部分,用于通过选择性地使用通用寄存器部分和专用寄存器部分之一的读出结果,基于来自解码器的解码结果执行预定处理。 解码器的解码操作,通用寄存器部分的读出操作和专用寄存器部分的读出操作被并行地执行。

    Processing device for buffering sequential and target sequences and target address information for multiple branch instructions
    6.
    发明授权
    Processing device for buffering sequential and target sequences and target address information for multiple branch instructions 失效
    用于缓冲顺序和目标序列的处理设备以及多个分支指令的目标地址信息

    公开(公告)号:US07134004B1

    公开(公告)日:2006-11-07

    申请号:US09666853

    申请日:2000-09-20

    IPC分类号: G06F9/00

    摘要: An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.

    摘要翻译: 信息处理装置通过流水线处理从指令存储部分读取,缓冲,解码和执行指令,包括:向指令存储部分分配读取地址的指令读取请求部分,包括多个指令缓冲器的指令缓冲部分, 缓冲从指令存储部分读取的指令序列; 指令执行单元,其对由指令缓冲部分缓冲的指令进行解码和执行。 分支指令检测部分检测从指令存储部分读取的指令序列中的分支指令。 分支目标地址信息缓冲部分包括多个分支目标地址信息缓冲器,当分支指令检测部分已经检测到分支指令时,缓冲用于生成分支指令的分支目标地址的转移目标地址信息。

    Memory controller and a cache for accessing a main memory, and a system and a method for controlling the main memory
    7.
    发明授权
    Memory controller and a cache for accessing a main memory, and a system and a method for controlling the main memory 有权
    用于访问主存储器的存储器控​​制器和缓存,以及用于控制主存储器的系统和方法

    公开(公告)号:US06542969B1

    公开(公告)日:2003-04-01

    申请号:US09332883

    申请日:1999-06-15

    申请人: Taizo Sato

    发明人: Taizo Sato

    IPC分类号: G06F1200

    CPC分类号: G06F12/0804 G06F12/0215

    摘要: A memory control system has a replacement detection/notification circuit for detecting occurrence of replacement of dirty entry in a cache and informing a memory controller of the detection, and a state control circuit for precharging the currently active page in a main memory when the memory controller is informed of the detection and a preceding access to the main memory attendant upon the replacement of dirty entry is completed. By precharging the active page in the main memory to return to the idle state when the preceding access attendant upon the replacement of dirty entry is completed, the succeeding access can be done only by activating the aimed page probably different from the above page. It is thereby obviated to return the activated page due to the preceding access to the idle state after a page miss occurs in the succeeding access.

    摘要翻译: 存储器控制系统具有替换检测/通知电路,用于检测高速缓存中的脏条目的替换的发生以及通知存储器控制器的检测;以及状态控制电路,用于在存储器控制器中向主存储器预充电当前活动页面 被通知检测,并且在更换脏条目时完成对主存储器的先前访问。 通过在主存储器中预先充电活动页面以返回到空闲状态,当更换脏条目时前一访问服务器完成时,只有通过激活可能不同于上述页面的目标页面才能完成后续访问。 由于在后续访问中发生页错误之后,由于上述访问空闲状态而无法返回激活的页面。