公开(公告)号：US06414883B2

公开(公告)日：2002-07-02

申请号：US09860795

申请日：2001-05-21

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：USRE36089E

公开(公告)日：1999-02-09

申请号：US652008

申请日：1996-05-23

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US5426615A

公开(公告)日：1995-06-20

申请号：US224461

申请日：1994-04-07

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C5/02

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band comprising a plurality of sense amplifiers, and a plurality of power supply and ground lines arranged in a meshed shape. Power supply and ground lines include lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to a power supply and ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. Each drive component is provided for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of power supply and ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potential is generated to allow a stable supply of a power supply and ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to proximate power supply and ground lines through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带以及以网状形状布置的多个电源和接地线。 电源和接地线包括与感测放大器带平行并接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到布置在感测放大器附近并与其平行布置的电源和接地线。 每个驱动部件被提供用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 布置成网状的多个电源和接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的电源和接地线，所以无论感测放大器驱动信号线的长度如何，都可以进行可靠且高速的感测操作。

公开(公告)号：US5321646A

公开(公告)日：1994-06-14

申请号：US865142

申请日：1992-04-08

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi

IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4074 ,  G11C5/02 ,  G11C8/00

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C7/065

摘要： A power supply line is disposed parallel to a sense amplifier train including a plurality of sense amplifiers at the side of each subarray. The power supply line is connected to the sense amplifier included in the sense amplifier train via a plurality of drive transistors and a sense amplifier drive line.

摘要翻译： 电源线平行于包括在每个子阵列一侧的多个读出放大器的读出放大器串列布置。 电源线通过多个驱动晶体管和读出放大器驱动线路连接到包括在读出放大器列中的读出放大器。

公开(公告)号：US06859403B2

公开(公告)日：2005-02-22

申请号：US10815798

申请日：2004-04-02

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

摘要翻译： 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

公开(公告)号：US06272055B1

公开(公告)日：2001-08-07

申请号：US09168962

申请日：1998-10-09

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US5943273A

公开(公告)日：1999-08-24

申请号：US899143

申请日：1997-07-23

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

公开(公告)号：US5687123A

公开(公告)日：1997-11-11

申请号：US312968

申请日：1994-09-30

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

摘要翻译： 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

公开(公告)号：US5602793A

公开(公告)日：1997-02-11

申请号：US417527

申请日：1995-04-06

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potentials is generated to allow a stable supply of a power supply potential and a ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to a proximate operation power supply potential line and ground line through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带，以及以网状形状布置的多个操作电源电位线和多个接地电位线。 操作电源电位线和接地电位线包括与感测放大器频带平行并且接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到操作电源电位线和布置在感测放大器附近并与之并联的接地线。 驱动部件被设置用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 多个操作电源电位线和布置成网状的多个接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源电位和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的操作电源电位线和接地线，所以可靠且高速的感测操作是可能的，而与感测放大器驱动信号线的长度无关。

公开(公告)号：US5325336A

公开(公告)日：1994-06-28

申请号：US942320

申请日：1992-09-10

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band comprising a plurality of sense amplifiers, and a plurality of power supply and ground lines arranged in a meshed shape. Power supply and ground lines includes lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to a power supply and ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. Each drive component is provided for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of power supply and ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potential is generated to allow a stable supply of power supply and ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to proximate power supply and ground lines through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带以及以网状形状布置的多个电源和接地线。 电源和接地线包括与感测放大器频带平行并且接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到布置在感测放大器附近并与其平行布置的电源和接地线。 每个驱动部件被提供用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 布置成网状的多个电源和接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的电源和接地线，所以无论感测放大器驱动信号线的长度如何，都可以进行可靠且高速的感测操作。