公开(公告)号：US06826109B2

公开(公告)日：2004-11-30

申请号：US10345186

申请日：2003-01-16

申请人： Shigeru Nakahara ,  Satoshi Iwahashi ,  Takeshi Suzuki ,  Keiichi Higeta ,  Kazuo Kanetani

发明人： Shigeru Nakahara ,  Satoshi Iwahashi ,  Takeshi Suzuki ,  Keiichi Higeta ,  Kazuo Kanetani

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/104

摘要： The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.

摘要翻译： 本发明提供了一种半导体集成电路装置，其上安装有能够选择适于提高易用性，易于使用或低功耗或选择输入设定值的操作模式的RAM宏。 在RAM宏的第一操作模式中，接收输入信号的定时被设置为第一定时。 在第二操作模式中，将接收输入信号的定时设置为晚于第一定时的第二定时。 在包括用于接收输入信号的输入电路和用于对输入电路的输出信号进行解码的解码器电路的半导体集成电路装置中，基于第一信号激活输入电路，并且解码器电路基于 的第二信号。

公开(公告)号：US07012848B2

公开(公告)日：2006-03-14

申请号：US10917320

申请日：2004-08-13

申请人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C7/00

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C8/16 ,  G11C11/4125

摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.

公开(公告)号：US20050013159A1

公开(公告)日：2005-01-20

申请号：US10917320

申请日：2004-08-13

申请人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C11/419 ,  G11C7/10 ,  G11C8/16 ,  G11C11/41 ,  G11C11/417 ,  G11C11/00

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C8/16 ,  G11C11/4125

摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.

摘要翻译： 本发明提供了一种新型的半导体集成电路装置，其具有存储电路，高速存储器和大容量存储电路，能够加速和促进定时设定。 半导体集成电路器件设有第一放大电路; 其包括第一导电类型的第一MOSFET，其具有为存储单元分别连接的多个位线提供的栅极，并且分别在提供给位线的预充电电压下分别保持在截止状态，作为读取电路 存储器单元根据选择字线和存储器信息的操作确定存储器电流是否流动; 并且分别与用于位线的选择信号相关联地进入操作状态，并且还设置有第二放大器电路，其包括： 多个第二导电类型的第二MOSFET，其分别具有分别被提供有第一放大器电路的多个放大信号并且以并联配置连接的栅极; 并且其形成对应于第一放大器电路的放大信号的放大信号。

公开(公告)号：US06795368B2

公开(公告)日：2004-09-21

申请号：US10734249

申请日：2003-12-15

申请人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C700

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C8/16 ,  G11C11/4125

摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.

公开(公告)号：US06707751B2

公开(公告)日：2004-03-16

申请号：US10339339

申请日：2003-01-10

申请人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

发明人： Satoshi Iwahashi ,  Shigeru Nakahara ,  Takeshi Suzuki ,  Keiichi Higeta

IPC分类号： G11C700

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C8/16 ,  G11C11/4125

摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.

公开(公告)号：US20050146947A1

公开(公告)日：2005-07-07

申请号：US11011427

申请日：2004-12-15

申请人： Keiichi Higeta ,  Satoshi Iwahashi ,  Yoichiro Aihara ,  Shigeru Nakahara

发明人： Keiichi Higeta ,  Satoshi Iwahashi ,  Yoichiro Aihara ,  Shigeru Nakahara

IPC分类号： G11C15/04 ,  G11C16/04 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  G11C15/04 ,  G11C15/043 ,  H01L27/1104

摘要： Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.

摘要翻译： 数据线（D 0，D 1）由第一存储部分（MA）和第二存储部分（MB）共享，此外，第一晶体管（MC 0）耦合到第一比较数据部分（CD 0）和 耦合到第一存储部分的存储节点的第二晶体管（MCA）串联连接以形成第一比较电路（11）和耦合到第二比较数据线（CD 1）的第三晶体管（MC 1）和 耦合到第二存储部分的存储节点的第四晶体管（MCB）串联连接以形成第二比较电路（12）。 因此，可以提高扩散层和布线层的布局的对称性，并且实现存储单元相对于穿过其中心的中心线线对称的布局的容易性。 因此，可以容易地优化制造工艺条件，并且可以降低制造工艺的变化，从而可以实现存储单元的微细加工。

公开(公告)号：US07009862B2

公开(公告)日：2006-03-07

申请号：US11011427

申请日：2004-12-15

申请人： Keiichi Higeta ,  Satoshi Iwahashi ,  Yoichiro Aihara ,  Shigeru Nakahara

发明人： Keiichi Higeta ,  Satoshi Iwahashi ,  Yoichiro Aihara ,  Shigeru Nakahara

IPC分类号： G11C7/00

CPC分类号： H01L27/11 ,  G11C15/04 ,  G11C15/043 ,  H01L27/1104

摘要： Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.

摘要翻译： 数据线（D 0，D 1）由第一存储部分（MA）和第二存储部分（MB）共享，此外，第一晶体管（MC 0）耦合到第一比较数据部分（CD 0）和 耦合到第一存储部分的存储节点的第二晶体管（MCA）串联连接以形成第一比较电路（11）和耦合到第二比较数据线（CD 1）的第三晶体管（MC 1）和 耦合到第二存储部分的存储节点的第四晶体管（MCB）串联连接以形成第二比较电路（12）。 因此，可以提高扩散层和布线层的布局的对称性，并且实现存储单元相对于穿过其中心的中心线线对称的布局的容易性。 因此，可以容易地优化制造工艺条件，并且可以降低制造工艺的变化，从而可以实现存储单元的微细加工。

公开(公告)号：US06856574B2

公开(公告)日：2005-02-15

申请号：US10720118

申请日：2003-11-25

申请人： Satoshi Iwahashi ,  Keiichi Higeta

发明人： Satoshi Iwahashi ,  Keiichi Higeta

IPC分类号： G11C11/417 ,  G11C7/22 ,  G11C11/41 ,  G11C11/413 ,  G11C8/00

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/413

摘要： A semiconductor memory device comprises a memory-cell array for storing data, a peripheral circuit for carrying out an operation to read out or write data from or into the memory-cell array, read clock generation circuits (111, 113 and 115) each used for generating a read clock signal to be supplied to the peripheral circuit in the operation to read out data from the memory-cell array, write clock generation circuits (112, 114 and 116) each used for generating a write clock signal to be supplied to the peripheral circuit in the operation to write data into the memory-cell array. Since the pulse widths of the clock signals in read and writes are adjusted individually, margin insufficiencies of the pulse widths can be evaluated and results of the evaluation can be fed back to a design phase for, among other purposes, correction of a layout.

摘要翻译： 半导体存储器件包括用于存储数据的存储单元阵列，用于执行从存储单元阵列读出数据或从其写入数据的操作的外围电路，每个使用的读时钟生成电路（111,113和115） 用于在用于从存储单元阵列读出数据的操作中产生要提供给外围电路的读取时钟信号;写入时钟生成电路（112,114和116），每个用于产生要提供给写入时钟信号的时钟生成电路 外围电路在操作中将数据写入存储单元阵列。 由于读取和写入中的时钟信号的脉冲宽度被单独调整，所以可以评估脉冲宽度的余量不足，并且可以将评估结果反馈到设计阶段，以用于布局的校正。