公开(公告)号：US06826109B2

公开(公告)日：2004-11-30

申请号：US10345186

申请日：2003-01-16

申请人： Shigeru Nakahara ,  Satoshi Iwahashi ,  Takeshi Suzuki ,  Keiichi Higeta ,  Kazuo Kanetani

发明人： Shigeru Nakahara ,  Satoshi Iwahashi ,  Takeshi Suzuki ,  Keiichi Higeta ,  Kazuo Kanetani

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/104

摘要： The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.

摘要翻译： 本发明提供了一种半导体集成电路装置，其上安装有能够选择适于提高易用性，易于使用或低功耗或选择输入设定值的操作模式的RAM宏。 在RAM宏的第一操作模式中，接收输入信号的定时被设置为第一定时。 在第二操作模式中，将接收输入信号的定时设置为晚于第一定时的第二定时。 在包括用于接收输入信号的输入电路和用于对输入电路的输出信号进行解码的解码器电路的半导体集成电路装置中，基于第一信号激活输入电路，并且解码器电路基于 的第二信号。

公开(公告)号：US06369617B1

公开(公告)日：2002-04-09

申请号：US09437268

申请日：1999-11-10

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

IPC分类号： G11C800

CPC分类号： G11C8/10

摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

摘要翻译： 为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主解码器都包括半导体逻辑电路，其中列数 用于下拉输出节点的晶体管即使输入数量大也很小，并且获得具有大致相同延迟时间的真实输出信号和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为 减少 通过这种布置，解码器电路的工作可以加快，可以降低功耗，可以提高周期，并且在半导体存储器中，例如可以减少访问时间和功耗，并且增加 的周期被启用。

公开(公告)号：US06807115B2

公开(公告)日：2004-10-19

申请号：US10360867

申请日：2003-02-10

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Keiichi Higeta

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Keiichi Higeta

IPC分类号： G11C700

CPC分类号： G01R31/31701

摘要： In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

摘要翻译： 在每个周期执行预充电和评估操作的动态型半导体集成电路中，可以在评估期间进行IDDQ测试和光检测测试，以便于诊断和故障分析，从而提高测试精度。 动态型半导体集成电路在正常操作模式或测试模式下工作，其中其间的开关由模式选择信号触发。 在正常工作模式中，内部激活信号的脉冲宽度被控制为恒定的，即，以操作周期时间长度不变。 在测试模式中，内部激活信号的脉冲宽度被控制以根据操作周期时间长度而变化。

公开(公告)号：US06677782B2

公开(公告)日：2004-01-13

申请号：US09840190

申请日：2001-04-24

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

IPC分类号： H03K19096

CPC分类号： G11C8/10

摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. According to the present invention, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and in a semiconductor memory for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

摘要翻译： 为了加快解码电路的运行，解码电路的功耗降低，周期增加，解码电路中的缓冲器，预解码器，主译码器等电路由半导体逻辑电路构成， 用于在输出节点下拉的晶体管的列较小，即使输入数量多，并且获得具有大致相同延迟时间的真实和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为 根据本发明，可以加速解码器电路的操作，可以降低功耗，可以增加周期，并且在半导体存储器中，例如，减少访问时间和功耗以及增加 的周期被启用。

公开(公告)号：US06998878B2

公开(公告)日：2006-02-14

申请号：US10754596

申请日：2004-01-12

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

IPC分类号： H03K19/20

CPC分类号： G11C8/10

摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.

摘要翻译： 为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主译码器都包括半导体逻辑电路，其中， 在输出节点下拉的晶体管列很小，即使输入数量很多，并且获得了真实的和具有大致相同延迟时间的互补输出信号，并且解码器电路中每个电路的输出脉冲长度是 减少 利用这种布置，可以加速解码器电路的操作，可以降低功耗，可以提高周期，例如，在半导体存储器中，可以减少访问时间和功耗，并且可以将周期 增加。

公开(公告)号：US06617610B2

公开(公告)日：2003-09-09

申请号：US10013474

申请日：2001-12-13

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Keiichi Higeta

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Keiichi Higeta

IPC分类号： H01L2358

CPC分类号： G01R31/31701

摘要： In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

公开(公告)号：US6075729A

公开(公告)日：2000-06-13

申请号：US145161

申请日：1998-09-01

申请人： Kenichi Ohhata ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki ,  Keiichi Higeta

发明人： Kenichi Ohhata ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki ,  Keiichi Higeta

IPC分类号： G11C7/12 ,  G11C11/412 ,  G11C7/00

CPC分类号： G11C11/412 ,  G11C7/12 ,  G11C2207/12

摘要： A semiconductor memory has a plurality of word lines a plurality of bit line pairs and a plurality of memory cells formed at intersection points between the word lines and the bit line pairs. A word decoder generates a word line select signal upon receipt of an address signal and a bit decoder generates a bit line select signal on receiving the address signal. A bit line load circuit receives a signal current from the applicable memory cell, a sense circuit detects an output signal from the bit line load circuit, and a bit line pull-down circuit and a bit line recovery circuit drives the applicable bit lines upon writing data to the memory cell in question. The bit line load circuit and the bit line recovery circuit include pMOS transistors whose drains are connected to the bit lines and whose gates are fed with a control signal, and diodes whose anodes are connected to a first power supply and whose cathodes are connected to sources of the pMOS transistors, the pMOS transistors and the diodes being furnished to each of the bit line pairs. The pMOS transistors are inhibited from conducting while the bit lines are being driven Low by the bit line pull-down circuit during a write cycle, and allowed to conduct during other periods including a read cycle. This constitution shortens the recovery time, implementing a high-speed SRAM with a shortened cycle time.

摘要翻译： 半导体存储器具有多个字线，多个位线对和形成在字线和位线对之间的交点处的多个存储单元。 字解码器在接收到地址信号时产生字线选择信号，并且位解码器在接收到地址信号时产生位线选择信号。 位线负载电路从可应用的存储单元接收信号电流，感测电路检测来自位线负载电路的输出信号，位线下拉电路和位线恢复电路在写入时驱动可应用的位线 数据到所讨论的存储单元。 位线负载电路和位线恢复电路包括其漏极连接到位线并且其栅极被馈送控制信号的pMOS晶体管，以及其阳极连接到第一电源并且其阴极连接到源极的二极管 的pMOS晶体管，pMOS晶体管和二极管被提供给每个位线对。 在写周期期间位线被位线下拉电路驱动为低电平时，禁止pMOS晶体管导通，并允许其在包括读周期的其他周期期间导通。 这种结构缩短了恢复时间，实现了一个缩短周期时间的高速SRAM。

公开(公告)号：US06316961B2

公开(公告)日：2001-11-13

申请号：US09725812

申请日：2000-11-30

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

IPC分类号： H03K19096

CPC分类号： H03K19/0963 ,  H03K19/1738

摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

公开(公告)号：US5398201A

公开(公告)日：1995-03-14

申请号：US53330

申请日：1993-04-28

申请人： Hiroaki Nambu ,  Noriyuki Homma ,  Kunihiko Yamaguchi ,  Hisayuki Higuchi ,  Kazuo Kanetani ,  Youji Idei ,  Ken'ichi Ohata ,  Yoshiaki Sakurai ,  Masanori Odaka ,  Goro Kitsukawa

发明人： Hiroaki Nambu ,  Noriyuki Homma ,  Kunihiko Yamaguchi ,  Hisayuki Higuchi ,  Kazuo Kanetani ,  Youji Idei ,  Ken'ichi Ohata ,  Yoshiaki Sakurai ,  Masanori Odaka ,  Goro Kitsukawa

IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C11/34

CPC分类号： G11C7/1057 ,  G11C5/147 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

摘要： A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.

摘要翻译： 一种适于实现存储器的高速的电路技术，其以使得存储器单元包括场效应晶体管和外围电路的方式构造，包括双极晶体管和场效应晶体管。 根据本发明，将集电极连接到差分放大器并根据输入到基极或发射极的信号向差分放大器提供电流的双极晶体管和双极晶体管，以提供电流 只有写入位线才能连接。 根据本发明，通过切换选择位线来读取信息时的访问时间的高速度被实现。 此外，当写入信息时位线的充电/放电时间减少，并且也可以实现高速的写入时间。 还公开了字线和位线的驱动器的改进，并且可以实现可以作为整个半导体存储器以高速度操作的半导体存储器。

公开(公告)号：US07685455B2

公开(公告)日：2010-03-23

申请号：US11936543

申请日：2007-11-07

申请人： Hiroaki Nambu ,  Masao Shinozaki ,  Kazuo Kanetani ,  Hideto Kazama

发明人： Hiroaki Nambu ,  Masao Shinozaki ,  Kazuo Kanetani ,  Hideto Kazama

IPC分类号： G06F1/04

CPC分类号： G11C11/413 ,  G06F1/04 ,  G11C11/419

摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

摘要翻译： 提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。 半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。 产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。