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公开(公告)号:US20080224751A1
公开(公告)日:2008-09-18
申请号:US12047162
申请日:2008-03-12
申请人: Shigetaka ASANO , Kazuyoshi Kikuta
发明人: Shigetaka ASANO , Kazuyoshi Kikuta
IPC分类号: H03H11/26
CPC分类号: H03K5/133 , H03K2005/00026 , H03K2005/00058
摘要: A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.
摘要翻译: 一种延迟电路,包括:串联耦合的多个第一延迟单元,每个被配置为产生大约是单位延迟时间的两倍的延迟时间; 第二延迟单元,被配置为产生所述单位延迟时间并耦合到所述多个第一延迟单元的最后一级; 以及选择器,其被配置为选择所述多个第一延迟单元的最后级的输出信号或所述第二延迟单元的输出信号,其中外部输入信号被输入到所述第一延迟单元和每个第二延迟单元, 并且第一延迟单元和第二延迟单元各自包括被配置为延迟输出前级延迟单元的输出信号或外部输入信号的开关电路。
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2.
公开(公告)号:US20100321078A1
公开(公告)日:2010-12-23
申请号:US12817692
申请日:2010-06-17
申请人: Shigetaka ASANO
发明人: Shigetaka ASANO
CPC分类号: H03K7/08
摘要: A timing controller includes a controller that controls an operation timing of a controlled unit, and a setting unit that associates a timing obtained by dividing a setting of the operation timing into a plurality of timings, each timing having an identification number, and sets the control unit so that an offset period based on the associated timing is added to the operation timing of the controlled unit.
摘要翻译: 定时控制器包括:控制器,其控制受控单元的操作定时;以及设定单元,其将通过将所述操作定时的设定除以多个定时获得的定时,每个定时具有识别号,并且设置所述控制 使得基于相关联的定时的偏移周期被添加到受控单元的操作定时。
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公开(公告)号:US20080224747A1
公开(公告)日:2008-09-18
申请号:US12042776
申请日:2008-03-05
申请人: Shigetaka ASANO
发明人: Shigetaka ASANO
CPC分类号: H03L7/0812 , H03K5/133 , H03K2005/00026 , H03L7/0805
摘要: Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.
摘要翻译: 这里公开了一种可变延迟电路,包括延迟输入信号的第一延迟部分; 输出部分 以及耦合在第一延迟部分和输出部分之间的可变阻抗部分。
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