公开(公告)号：US6101596A

公开(公告)日：2000-08-08

申请号：US894924

申请日：1997-09-03

申请人： Shigeya Tanaka ,  Kotaro Shimamura ,  Tetsuya Shimomura ,  Takashi Hotta ,  Hideo Sawamoto

发明人： Shigeya Tanaka ,  Kotaro Shimamura ,  Tetsuya Shimomura ,  Takashi Hotta ,  Hideo Sawamoto

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3838 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859

摘要： An information processor is capable of eliminating register conflict in short and long latency processes and for attaining high-speed pipeline processing through efficient use of registers. The scale of the necessary hardware is reduced by the processor using a register conflict detector and a scoreboard. The register conflict detector detects register conflict over a period of short latency processing, and the scoreboard checks for register conflict beyond the short latency process period and into a period of long latency processing. The processor controls the issue of instructions based on the detected register conflict status.

摘要翻译： PCT No.PCT / JP95 / 00356 Sec。 371日期：1997年9月3日 102（e）日期1997年9月3日PCT Filed Mar. 6，1995 PCT Pub。 公开号WO96 / 27833 日期1996年9月12日信息处理器能够消除短延时和长延迟过程中的寄存器冲突，并通过有效使用寄存器实现高速流水线处理。 处理器使用寄存器冲突检测器和记分板来减少所需硬件的规模。 寄存器冲突检测器在短时延处理期间检测寄存器冲突，并且记分板检查超出短延迟处理周期的寄存器冲突并进入长延迟处理期间。 处理器根据检测到的寄存器冲突状态控制指令的问题。

公开(公告)号：US20070233959A1

公开(公告)日：2007-10-04

申请号：US11802944

申请日：2007-05-29

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

公开(公告)号：US20050102472A1

公开(公告)日：2005-05-12

申请号：US11014885

申请日：2004-12-20

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

公开(公告)号：US06275902B1

公开(公告)日：2001-08-14

申请号：US09188693

申请日：1998-11-10

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F1208

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US07240159B2

公开(公告)日：2007-07-03

申请号：US11014885

申请日：2004-12-20

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/02

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US06848027B2

公开(公告)日：2005-01-25

申请号：US10426828

申请日：2003-05-01

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US06587927B2

公开(公告)日：2003-07-01

申请号：US09864287

申请日：2001-05-25

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F1208

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

公开(公告)号：US5848432A

公开(公告)日：1998-12-08

申请号：US281002

申请日：1994-07-27

申请人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

发明人： Takashi Hotta ,  Toshihiko Kurihara ,  Shigeya Tanaka ,  Hideo Sawamoto ,  Akiyoshi Osumi ,  Koji Saito ,  Kotaro Shimamura

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6028

摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

摘要翻译： 数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。 经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。 高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。 基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

公开(公告)号：US6032229A

公开(公告)日：2000-02-29

申请号：US562187

申请日：1995-11-22

申请人： Takashi Hotta ,  Hideo Sawamoto ,  Noboru Akiyama ,  Takashi Akioka ,  Shigeya Tanaka

发明人： Takashi Hotta ,  Hideo Sawamoto ,  Noboru Akiyama ,  Takashi Akioka ,  Shigeya Tanaka

IPC分类号： G06F12/00 ,  G06F12/08 ,  G11C11/401 ,  G11C11/407 ,  G06F13/00

CPC分类号： G06F12/0855

摘要： An information processor having a high performance as a whole is provided by improving the throughput of the processor and the semiconductor memory device. The information processor comprises a memory having a buffer for temporarily holding data and a processor having a memory interface part for controlling the memory to transfer data to the buffer before determining whether the data is to be written in the memory and to write the data in said memory after determining of writing. Data writing and reading to the semiconductor device is pipelined by justifying data exchange between reading and writing. Since the data transfer timings of reading from a memory and writing in the memory can be executed at the same time, the reading process and the writing process can be performed by pipeline-like process and the throughput can be improved.

摘要翻译： 通过提高处理器和半导体存储器件的吞吐量来提供整体上具有高性能的信息处理器。 信息处理器包括具有用于临时保存数据的缓冲器的存储器和具有存储器接口部分的处理器，该存储器接口部分用于在确定数据是否被写入存储器之前控制存储器将数据传送到缓冲器，并将数据写入所述存储器 记忆确定写作后。 通过调整阅读和写入之间的数据交换，对半导体器件的数据写入和读取进行流水线化。 由于可以同时执行从存储器的读取和写入的数据传送定时，因此可以通过流水线的处理来执行读取处理和写入处理，并且可以提高吞吐量。

公开(公告)号：US6101627A

公开(公告)日：2000-08-08

申请号：US206153

申请日：1998-12-07

申请人： Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

发明人： Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

IPC分类号： G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F11/30 ,  G06F13/00 ,  G06F15/78 ,  H02H3/05 ,  G06F7/02 ,  G06F11/08

CPC分类号： G06F11/1637 ,  G06F11/1654 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2043

摘要： An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective ones result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

摘要翻译： 信息处理系统具有多个处理器电路，每个处理器电路包括内部电路和内部处理结果输出电路，该系统具有连接到每个处理器电路的内部数据选择电路和至少一个故障检测电路。 每个处理器电路的内部处理结果输出电路输出由处理器电路中的各个内部电路处理的各个结果数据。 每个内部数据选择电路在预定的定时选择并输出从每个处理器电路的内部处理结果输出电路输出的一个选择的结果数据。 故障检测电路输出由处理器电路的各个内部数据选择电路选择的数据或由处理器电路在每个预定定时输出的数据之间的比较结果。