公开(公告)号：US06792493B2

公开(公告)日：2004-09-14

申请号：US10337758

申请日：2003-01-07

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

IPC分类号： G06F1300

CPC分类号： G06F13/4068 ,  G06F12/0292 ,  G06F12/06 ,  G06F13/385 ,  G06F13/4243

摘要： A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and parallelly controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

摘要翻译： 一种包括总线状态控制器并用于个人计算机等的微处理器。 总线状态控制器包括诸如等待控制器的控制寄存器，并且并行地控制各种半导体存储器（ROM，突发ROM，SRAM，PSRAM，DRAM和同步RAM）和PC卡（存储器和I / O卡）的接口。 总线状态控制器中还包括控制寄存器，用于控制设置同步DRAM的PC卡启动信号的时间。 微处理器的外部总线的地址空间被分成预定数量的半导体存储器和PC卡固定分配的区域。 微处理器还包括用于将内部准备的逻辑地址转换为物理地址的存储器管理单元。

公开(公告)号：US6049844A

公开(公告)日：2000-04-11

申请号：US191219

申请日：1998-11-13

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4068 ,  G06F12/06 ,  G06F13/385 ,  G06F13/4243 ,  G06F12/0292

摘要： A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

摘要翻译： 一种包括总线状态控制器并用于个人计算机等的微处理器。 总线状态控制器包括诸如等待控制器的控制寄存器，并且并行控制各种半导体存储器（ROM，突发ROM，SRAM，PSRAM，DRAM和同步RAM）和PC卡（存储器和I / O卡）的接口。 总线状态控制器中还包括控制寄存器，用于控制设置同步DRAM的PC卡启动信号的时间。 微处理器的外部总线的地址空间被分成预定数量的半导体存储器和PC卡固定分配的区域。 微处理器还包括用于将内部准备的逻辑地址转换为物理地址的存储器管理单元。

公开(公告)号：US5848247A

公开(公告)日：1998-12-08

申请号：US524701

申请日：1995-09-07

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4068 ,  G06F12/06 ,  G06F13/385 ,  G06F13/4243 ,  G06F12/0292

摘要： A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

摘要翻译： 一种包括总线状态控制器并用于个人计算机等的微处理器。 总线状态控制器包括诸如等待控制器的控制寄存器，并且并行控制各种半导体存储器（ROM，突发ROM，SRAM，PSRAM，DRAM和同步RAM）和PC卡（存储器和I / O卡）的接口。 总线状态控制器中还包括控制寄存器，用于控制设置同步DRAM的PC卡启动信号的时间。 微处理器的外部总线的地址空间被分成预定数量的半导体存储器和PC卡固定分配的区域。 微处理器还包括用于将内部准备的逻辑地址转换为物理地址的存储器管理单元。

公开(公告)号：US06594720B1

公开(公告)日：2003-07-15

申请号：US09438337

申请日：1999-11-13

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

IPC分类号： G06F1300

CPC分类号： G06F13/4068 ,  G06F12/0292 ,  G06F12/06 ,  G06F13/385 ,  G06F13/4243

摘要： A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and parallelly controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

摘要翻译： 一种包括总线状态控制器并用于个人计算机等的微处理器。 总线状态控制器包括诸如等待控制器的控制寄存器，并且并行地控制各种半导体存储器（ROM，突发ROM，SRAM，PSRAM，DRAM和同步RAM）和PC卡（存储器和I / O卡）的接口。 总线状态控制器中还包括控制寄存器，用于控制设置同步DRAM的PC卡启动信号的时间。 微处理器的外部总线的地址空间被分成预定数量的半导体存储器和PC卡固定分配的区域。 微处理器还包括用于将内部准备的逻辑地址转换为物理地址的存储器管理单元。

公开(公告)号：US5774701A

公开(公告)日：1998-06-30

申请号：US500227

申请日：1995-07-10

申请人： Shigezumi Matsui ,  Mitsuyoshi Yamamoto ,  Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Susumu Kaneko ,  Kiyoshi Hasegawa

发明人： Shigezumi Matsui ,  Mitsuyoshi Yamamoto ,  Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Susumu Kaneko ,  Kiyoshi Hasegawa

IPC分类号： G06F1/08 ,  G06F1/04

CPC分类号： G06F1/08

摘要： A microprocessor incorporating a PLL circuit using a clock pulse having a relatively low frequency as an input clock signal of a reference frequency to form an oscillating pulse of a relatively high frequency by multiplying the input clock signal. In the microprocessor, the operation of the PLL circuit is stopped in the low-speed mode to supply the clock pulse of the relatively low frequency to the microprocessor as a system clock signal, and, in the high-speed mode, the PLL circuit is activated upon reception of an event requiring high-speed processing. Until the operation of the PLL circuit is stabilized and the request for high-speed processing comes, the above-mentioned clock pulse having the relatively low frequency is kept supplied continuously to the microprocessor as the system clock signal. This novel setup permits the high-speed switching of the microprocessor from the operating mode to the high-speed operating mode. Accordingly, the microprocessor may be kept operating until the output frequency of the PLL circuit is stabilized, thereby allowing the microprocessor to cope with an unpredictable situation such as the occurrence of a priority event or a failure.

摘要翻译： 一种微处理器，其使用具有相对较低频率的时钟脉冲的PLL电路作为参考频率的输入时钟信号，以通过乘以输入时钟信号来形成相对高频率的振荡脉冲。 在微处理器中，PLL电路的操作在低速模式下停止，以较低频率的时钟脉冲作为系统时钟信号供给微处理器，在高速模式下，PLL电路为 在接收到需要高速处理的事件时被激活。 直到PLL电路的操作稳定并且高速处理的请求到来之前，具有较低频率的上述时钟脉冲作为系统时钟信号被连续地提供给微处理器。 这种新颖的设置允许微处理器从操作模式到高速操作模式的高速切换。 因此，微处理器可以保持工作，直到PLL电路的输出频率稳定，从而允许微处理器处理诸如发生优先事件或故障的不可预知的情况。

公开(公告)号：US06425039B2

公开(公告)日：2002-07-23

申请号：US09450894

申请日：1999-11-29

申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

IPC分类号： G06F1332

CPC分类号： G06F9/32 ,  G06F9/30101

摘要： A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H′400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

摘要翻译： 通过读取寄存器VBR的向量基地址一次并通过向其中添加向量偏移（H'400）来获得与TLB未命中异常事件相关的异常处理程序的向量点。 通过向寄存器VBR的值（向量基地址）添加矢量偏移，以及通过读取得到的地址偏移的异常代码，获得与除了TLB未命中异常事件之外的异常事件相关的异常处理程序的向量点 寄存器EXPEVT或INTEVT的值一次被添加到所获得的向量点。 因此，处理被分支到所需的异常处理程序，以执行与除了TLB未命中异常事件之外的异常事件相关的异常事件处理。

公开(公告)号：US6038661A

公开(公告)日：2000-03-14

申请号：US524712

申请日：1995-09-07

申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

IPC分类号： G06F11/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/48 ,  G06F12/10

CPC分类号： G06F9/32 ,  G06F9/30101

摘要： A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H'400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

摘要翻译： 通过读取寄存器VBR的向量基地址一次并通过向其中添加向量偏移（H'400）来获得与TLB未命中异常事件相关的异常处理程序的向量点。 通过向寄存器VBR的值（向量基地址）添加矢量偏移，以及通过读取得到的地址偏移的异常代码，获得与除了TLB未命中异常事件之外的异常事件相关的异常处理程序的向量点 寄存器EXPEVT或INTEVT的值一次被添加到所获得的向量点。 因此，处理被分支到所需的异常处理程序，以执行与除了TLB未命中异常事件之外的异常事件相关的异常事件处理。

公开(公告)号：US5564041A

公开(公告)日：1996-10-08

申请号：US201488

申请日：1994-02-24

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Yoshiyuki Kondo ,  Kouji Hashimoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Yoshiyuki Kondo ,  Kouji Hashimoto

IPC分类号： G06F11/26 ,  G06F11/34 ,  G06F11/36 ,  G06F11/30 ,  G06F9/22

CPC分类号： G06F11/364 ,  G06F11/3636 ,  G06F11/3648 ,  G06F11/3652 ,  G06F11/261 ,  G06F11/34

摘要： A microprocessor having a buffer or memory capable of holding a plurality of instructions in advance of execution also functions to insert a special bus cycle amongst the instructions for outputting the internal information of the microprocessor to the outside in a predetermined operation mode at the time of each execution. The information inside of the microprocessor, which is to be outputted to the outside in the special bus cycle, is identified by the address of the executed instruction in a memory space, an instruction code or the code for identifying said executed instruction in the instruction group prefetched. In an emulation of the system using the instruction prefetch type microprocessor, as described above, what instruction has been executed can be easily known from the outside to effect an accurate emulation analysis and to facilitate the analysis of trace data thereby to improve debugging efficiency.

摘要翻译： 具有能够在执行之前保持多个指令的缓冲器或存储器的微处理器还用于在每个时刻以预定的操作模式在用于将微处理器的内部信息输出到外部的指令之间插入专用总线周期 执行。 要在专用总线周期中输出到外部的微处理器内部的信息由存储器空间中执行的指令的地址，指令代码或用于识别指令组中的所述执行指令的代码 预取 在使用指令预取型微处理器的系统的仿真中，如上所述，从外部可以容易地知道已经执行了哪些指令以实现精确的仿真分析，并且便于对跟踪数据的分析，从而提高调试效率。

公开(公告)号：US4954942A

公开(公告)日：1990-09-04

申请号：US272757

申请日：1988-11-17

申请人： Satoshi Masuda ,  Ikuya Kawasaki ,  Shigezumi Matsui

发明人： Satoshi Masuda ,  Ikuya Kawasaki ,  Shigezumi Matsui

IPC分类号： G06F11/28 ,  G06F11/26 ,  G06F11/34 ,  G06F11/36 ,  G06F12/08 ,  G06F12/10 ,  G06F15/78

CPC分类号： G06F11/3636 ,  G06F11/261 ,  G06F11/3471 ,  G06F11/348 ,  G06F11/3648 ,  G06F12/10

摘要： The microprocessor has an address converting buffer to convert logical addresses into physical addresses and a signal generator representing the timing for the microprocessor to retrieve conversion information from an external memory and write it into the address converting buffer. With this configuration, it is possible to determine the logical address from the physical address that was output to an external circuit, without the microprocessor outputting the logical address directly to the external circuit.

摘要翻译： 微处理器具有地址转换缓冲器以将逻辑地址转换为物理地址，以及信号发生器，其表示微处理器从外部存储器检索转换信息的定时，并将其写入地址转换缓冲器。 利用该配置，可以从输出到外部电路的物理地址确定逻辑地址，而无需微处理器将逻辑地址直接输出到外部电路。

公开(公告)号：US5278962A

公开(公告)日：1994-01-11

申请号：US531891

申请日：1990-06-01

申请人： Satoshi Masuda ,  Ikuya Kawasaki ,  Shigezumi Matsui

发明人： Satoshi Masuda ,  Ikuya Kawasaki ,  Shigezumi Matsui

IPC分类号： G06F11/28 ,  G06F11/26 ,  G06F11/34 ,  G06F11/36 ,  G06F12/08 ,  G06F12/10 ,  G06F15/78

CPC分类号： G06F11/3636 ,  G06F11/261 ,  G06F11/3471 ,  G06F11/348 ,  G06F11/3648 ,  G06F12/10

摘要： The microprocessor has an address converting buffer to convert logical addresses into physical addresses and a signal generator representing the timing for the microprocessor to retrieve conversion information from an external memory and write it into the address converting buffer. With this configuration, it is possible to determine the logical address from the physical address that was output to an external circuit, without the microprocessor outputting the logical address directly to the external circuit.

摘要翻译： 微处理器具有地址转换缓冲器以将逻辑地址转换为物理地址，以及信号发生器，其表示微处理器从外部存储器检索转换信息的定时，并将其写入地址转换缓冲器。 利用该配置，可以从输出到外部电路的物理地址确定逻辑地址，而无需微处理器将逻辑地址直接输出到外部电路。