公开(公告)号：US5774701A

公开(公告)日：1998-06-30

申请号：US500227

申请日：1995-07-10

申请人： Shigezumi Matsui ,  Mitsuyoshi Yamamoto ,  Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Susumu Kaneko ,  Kiyoshi Hasegawa

发明人： Shigezumi Matsui ,  Mitsuyoshi Yamamoto ,  Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Susumu Kaneko ,  Kiyoshi Hasegawa

IPC分类号： G06F1/08 ,  G06F1/04

CPC分类号： G06F1/08

摘要： A microprocessor incorporating a PLL circuit using a clock pulse having a relatively low frequency as an input clock signal of a reference frequency to form an oscillating pulse of a relatively high frequency by multiplying the input clock signal. In the microprocessor, the operation of the PLL circuit is stopped in the low-speed mode to supply the clock pulse of the relatively low frequency to the microprocessor as a system clock signal, and, in the high-speed mode, the PLL circuit is activated upon reception of an event requiring high-speed processing. Until the operation of the PLL circuit is stabilized and the request for high-speed processing comes, the above-mentioned clock pulse having the relatively low frequency is kept supplied continuously to the microprocessor as the system clock signal. This novel setup permits the high-speed switching of the microprocessor from the operating mode to the high-speed operating mode. Accordingly, the microprocessor may be kept operating until the output frequency of the PLL circuit is stabilized, thereby allowing the microprocessor to cope with an unpredictable situation such as the occurrence of a priority event or a failure.

摘要翻译： 一种微处理器，其使用具有相对较低频率的时钟脉冲的PLL电路作为参考频率的输入时钟信号，以通过乘以输入时钟信号来形成相对高频率的振荡脉冲。 在微处理器中，PLL电路的操作在低速模式下停止，以较低频率的时钟脉冲作为系统时钟信号供给微处理器，在高速模式下，PLL电路为 在接收到需要高速处理的事件时被激活。 直到PLL电路的操作稳定并且高速处理的请求到来之前，具有较低频率的上述时钟脉冲作为系统时钟信号被连续地提供给微处理器。 这种新颖的设置允许微处理器从操作模式到高速操作模式的高速切换。 因此，微处理器可以保持工作，直到PLL电路的输出频率稳定，从而允许微处理器处理诸如发生优先事件或故障的不可预知的情况。

公开(公告)号：US6038661A

公开(公告)日：2000-03-14

申请号：US524712

申请日：1995-09-07

申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

IPC分类号： G06F11/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/48 ,  G06F12/10

CPC分类号： G06F9/32 ,  G06F9/30101

摘要： A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H'400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

摘要翻译： 通过读取寄存器VBR的向量基地址一次并通过向其中添加向量偏移（H'400）来获得与TLB未命中异常事件相关的异常处理程序的向量点。 通过向寄存器VBR的值（向量基地址）添加矢量偏移，以及通过读取得到的地址偏移的异常代码，获得与除了TLB未命中异常事件之外的异常事件相关的异常处理程序的向量点 寄存器EXPEVT或INTEVT的值一次被添加到所获得的向量点。 因此，处理被分支到所需的异常处理程序，以执行与除了TLB未命中异常事件之外的异常事件相关的异常事件处理。

公开(公告)号：US06425039B2

公开(公告)日：2002-07-23

申请号：US09450894

申请日：1999-11-29

申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

IPC分类号： G06F1332

CPC分类号： G06F9/32 ,  G06F9/30101

摘要： A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H′400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

摘要翻译： 通过读取寄存器VBR的向量基地址一次并通过向其中添加向量偏移（H'400）来获得与TLB未命中异常事件相关的异常处理程序的向量点。 通过向寄存器VBR的值（向量基地址）添加矢量偏移，以及通过读取得到的地址偏移的异常代码，获得与除了TLB未命中异常事件之外的异常事件相关的异常处理程序的向量点 寄存器EXPEVT或INTEVT的值一次被添加到所获得的向量点。 因此，处理被分支到所需的异常处理程序，以执行与除了TLB未命中异常事件之外的异常事件相关的异常事件处理。

公开(公告)号：US6049844A

公开(公告)日：2000-04-11

申请号：US191219

申请日：1998-11-13

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4068 ,  G06F12/06 ,  G06F13/385 ,  G06F13/4243 ,  G06F12/0292

摘要： A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

摘要翻译： 一种包括总线状态控制器并用于个人计算机等的微处理器。 总线状态控制器包括诸如等待控制器的控制寄存器，并且并行控制各种半导体存储器（ROM，突发ROM，SRAM，PSRAM，DRAM和同步RAM）和PC卡（存储器和I / O卡）的接口。 总线状态控制器中还包括控制寄存器，用于控制设置同步DRAM的PC卡启动信号的时间。 微处理器的外部总线的地址空间被分成预定数量的半导体存储器和PC卡固定分配的区域。 微处理器还包括用于将内部准备的逻辑地址转换为物理地址的存储器管理单元。

公开(公告)号：US5848247A

公开(公告)日：1998-12-08

申请号：US524701

申请日：1995-09-07

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4068 ,  G06F12/06 ,  G06F13/385 ,  G06F13/4243 ,  G06F12/0292

摘要： A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

摘要翻译： 一种包括总线状态控制器并用于个人计算机等的微处理器。 总线状态控制器包括诸如等待控制器的控制寄存器，并且并行控制各种半导体存储器（ROM，突发ROM，SRAM，PSRAM，DRAM和同步RAM）和PC卡（存储器和I / O卡）的接口。 总线状态控制器中还包括控制寄存器，用于控制设置同步DRAM的PC卡启动信号的时间。 微处理器的外部总线的地址空间被分成预定数量的半导体存储器和PC卡固定分配的区域。 微处理器还包括用于将内部准备的逻辑地址转换为物理地址的存储器管理单元。

公开(公告)号：US06792493B2

公开(公告)日：2004-09-14

申请号：US10337758

申请日：2003-01-07

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

IPC分类号： G06F1300

CPC分类号： G06F13/4068 ,  G06F12/0292 ,  G06F12/06 ,  G06F13/385 ,  G06F13/4243

摘要： A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and parallelly controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

摘要翻译： 一种包括总线状态控制器并用于个人计算机等的微处理器。 总线状态控制器包括诸如等待控制器的控制寄存器，并且并行地控制各种半导体存储器（ROM，突发ROM，SRAM，PSRAM，DRAM和同步RAM）和PC卡（存储器和I / O卡）的接口。 总线状态控制器中还包括控制寄存器，用于控制设置同步DRAM的PC卡启动信号的时间。 微处理器的外部总线的地址空间被分成预定数量的半导体存储器和PC卡固定分配的区域。 微处理器还包括用于将内部准备的逻辑地址转换为物理地址的存储器管理单元。

公开(公告)号：US06594720B1

公开(公告)日：2003-07-15

申请号：US09438337

申请日：1999-11-13

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

IPC分类号： G06F1300

CPC分类号： G06F13/4068 ,  G06F12/0292 ,  G06F12/06 ,  G06F13/385 ,  G06F13/4243

摘要： A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and parallelly controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

摘要翻译： 一种包括总线状态控制器并用于个人计算机等的微处理器。 总线状态控制器包括诸如等待控制器的控制寄存器，并且并行地控制各种半导体存储器（ROM，突发ROM，SRAM，PSRAM，DRAM和同步RAM）和PC卡（存储器和I / O卡）的接口。 总线状态控制器中还包括控制寄存器，用于控制设置同步DRAM的PC卡启动信号的时间。 微处理器的外部总线的地址空间被分成预定数量的半导体存储器和PC卡固定分配的区域。 微处理器还包括用于将内部准备的逻辑地址转换为物理地址的存储器管理单元。

公开(公告)号：US5907867A

公开(公告)日：1999-05-25

申请号：US657231

申请日：1996-06-03

申请人： Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

发明人： Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

摘要： A semiconductor integrated circuit device such as a data processing device having a set-associative translation look-aside buffer (TLB). A plurality of address arrays each have a second field for storing the value representing a page size. The values read from the second fields are used to change the range of address comparison by comparators. A plurality of data arrays each have a second field for storing a bit position address designating either an intra-page address or a page number following a page size change. The values read from the second fields of the address arrays are used as the basis for second selectors to select either an address in a predetermined location of an externally input virtual address or the address read from each of the second fields of the data arrays. The selected address is output as a physical address.

摘要翻译： 一种半导体集成电路装置，例如具有集相关翻译后备缓冲器（TLB）的数据处理装置。 多个地址阵列各自具有用于存储表示页面大小的值的第二字段。 从第二个字段读取的值用于通过比较器更改地址比较范围。 多个数据阵列各自具有用于存储指定页面大小改变之后的页内地址或页码的位位置地址的第二字段。 从地址阵列的第二个字段读取的值被用作第二选择器选择外部输入的虚拟地址的预定位置的地址或从数据阵列的每个第二场读取的地址的基础。 所选地址作为物理地址输出。

公开(公告)号：US6047354A

公开(公告)日：2000-04-04

申请号：US7249

申请日：1998-01-14

申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G11C15/00

CPC分类号： G06F12/1036 ,  G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

摘要翻译： 能够支持多个页面大小而不增加芯片占用面积或功耗的数据处理器。 用于支持虚拟存储器的该数据处理器由具有共享其索引地址的多个存储体的集合关联型高速缓存存储器构成，其中可以为每个页面设置虚拟页面大小，并且其中包括要在每个页面之间共享的TLB 多个虚拟页面以各种方式设置。 该TLB具有用于锁存一对虚拟页码和物理页号的锁存字段。 要支持的虚拟页面的最大大小设置为最小大小的两倍，并且TLB的存储区号设置为不小于前者中两个的大小。

公开(公告)号：US5796978A

公开(公告)日：1998-08-18

申请号：US524561

申请日：1995-09-07

申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC分类号： G06F12/1036 ,  G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

摘要翻译： 能够支持多个页面大小而不增加芯片占用面积或功耗的数据处理器。 用于支持虚拟存储器的该数据处理器由具有共享其索引地址的多个存储体的集合关联型高速缓存存储器构成，其中可以为每个页面设置虚拟页面大小，并且其中包括要在每个页面之间共享的TLB 多个虚拟页面以各种方式设置。 该TLB具有用于锁存一对虚拟页码和物理页号的锁存字段。 要支持的虚拟页面的最大大小设置为最小大小的两倍，并且TLB的存储区号设置为不小于前者中两个的大小。