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180 条记录 (耗时 0.03 秒)

    Superstrate solar cell
    4.
    发明授权
    Superstrate solar cell 有权
    太阳能电池

    公开(公告)号：US08530263B2

    公开(公告)日：2013-09-10

    申请号：US13207058

    申请日：2011-08-10

    申请人： Wen-Chin Lee ,  Wen-Tsai Yen ,  Liang-Sheng Yu ,  Yung Sheng Chiu

    发明人： Wen-Chin Lee ,  Wen-Tsai Yen ,  Liang-Sheng Yu ,  Yung Sheng Chiu

    IPC分类号： H01L21/00 ,  H01L31/00

    CPC分类号： H01L31/1864 ,  H01L31/022425 ,  H01L31/046 ,  H01L31/0465 ,  Y02E10/50

    摘要： A method of fabricating a solar cell includes forming a front contact layer over a substrate, and the front contact layer is optically transparent at specified wavelengths and electrically conductive. A first scribed area is scribed through the front contact layer to expose a portion of the substrate. A buffer layer doped with an n-type dopant is formed over the front contact layer and the first scribed area. An absorber layer doped with a p-type dopant is formed over the buffer layer. A back contact layer that is electrically conductive is formed over the absorber layer.

    摘要翻译： 制造太阳能电池的方法包括在衬底上形成前接触层，并且前接触层在特定波长处是光学透明的并且是导电的。 通过前接触层划刻第一划线区域以暴露基板的一部分。 掺杂有n型掺杂剂的缓冲层形成在前接触层和第一划线区上。 在缓冲层上形成掺杂有p型掺杂剂的吸收层。 在吸收层上形成导电的背接触层。

    METHOD FOR FORMING THIN FILM SOLAR CELL WITH BUFFER-FREE FABRICATION PROCESS
    5.
    发明申请
    METHOD FOR FORMING THIN FILM SOLAR CELL WITH BUFFER-FREE FABRICATION PROCESS 审中-公开
    用无刷制造工艺形成薄膜太阳能电池的方法

    公开(公告)号：US20130118569A1

    公开(公告)日：2013-05-16

    申请号：US13295148

    申请日：2011-11-14

    申请人： Wen-Chin Lee ,  Liang-Sheng Yu ,  Wen-Tsai Yen ,  Yung-Sheng Chiu

    发明人： Wen-Chin Lee ,  Liang-Sheng Yu ,  Wen-Tsai Yen ,  Yung-Sheng Chiu

    IPC分类号： H01L31/0224 ,  H01L31/18

    CPC分类号： H01L31/0749 ,  H01L31/0322 ,  H01L31/0463 ,  Y02E10/541 ,  Y02P70/521

    摘要： A thin film solar cell and process for forming the same. The solar cell includes a bottom electrode layer, a light absorbing semiconductor layer, and top electrode layer. The absorber layer includes a p-type interior region and an n-type exterior region formed around the perimeter of the layer from a modified native portion of the p-type interior region, thereby forming an active n-p junction that is an intrinsic part of the absorber layer. The top electrode layer is electrically connected to the bottom electrode layer via a scribe line formed in the absorber layer that defines sidewalls. The n-type exterior region of the absorber layer extends along both the horizontal top of the absorber layer, and onto the vertical sidewalls of the scribe line to increase the area of available n-p junction in the solar cell thereby improving solar conversion efficiency.

    摘要翻译： 薄膜太阳能电池及其形成方法。 太阳能电池包括底部电极层，光吸收半导体层和顶部电极层。 吸收层包括p型内部区域和从p型内部区域的修饰的天然部分围绕该层的周边形成的n型外部区域，从而形成作为p型内部区域的固有部分的活性np结， 吸收层。 顶部电极层通过形成在限定侧壁的吸收体层中的划痕线电连接到底部电极层。 吸收层的n型外部区域沿着吸收层的水平顶部延伸，并且延伸到划线的垂直侧壁上，以增加太阳能电池中可用的n-p结的面积，从而提高太阳能转换效率。

    Methods for forming a transistor with a strained channel
    8.
    发明授权
    Methods for forming a transistor with a strained channel 有权
    用于形成具有应变通道的晶体管的方法

    公开(公告)号：US08236658B2

    公开(公告)日：2012-08-07

    申请号：US12477757

    申请日：2009-06-03

    申请人： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： A semiconductor device and method for fabricating a semiconductor device providing reduced short channel effects is disclosed. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate.

    摘要翻译： 公开了一种用于制造提供减小的短通道效应的半导体器件的半导体器件和方法。 该方法包括提供包括第一材料的基底; 在所述衬底上形成至少一个栅极堆叠; 在所述衬底中形成一个或多个凹槽，其中所述一个或多个凹部限定至少一个源极区域和至少一个漏极区域; 并且形成袋，包含第二材料的第一层和在所述一个或多个凹部中包含第三材料的第二层，所述袋设置在所述第一层和所述基底之间。

    Semiconductor device and a method of fabricating the device
    9.
    发明授权
    Semiconductor device and a method of fabricating the device 有权
    半导体装置及其制造方法

    公开(公告)号：US08154107B2

    公开(公告)日：2012-04-10

    申请号：US11703365

    申请日：2007-02-07

    申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L23/58

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.

    摘要翻译： 具有被超应力层覆盖的至少一个晶体管的半导体器件及其制造方法。 在NMOS器件中，超应力层包括源极和漏极区域上的拉伸应力膜，以及多个区域上的压应力膜。 在PMOS器件中，超应力层包括源极和漏极区域上的压缩应力膜和在多个区域上的拉伸应力膜。 在优选实施例中，半导体器件包括PMOS晶体管和形成CMOS器件并被超压应力层覆盖的NMOS晶体管。

    Tunnel Field-Effect Transistors with Superlattice Channels
    10.
    发明申请
    Tunnel Field-Effect Transistors with Superlattice Channels 有权
    具超晶格通道的隧道场效应晶体管

    公开(公告)号：US20110027959A1

    公开(公告)日：2011-02-03

    申请号：US12898421

    申请日：2010-10-05

    申请人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

    发明人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7391 ,  H01L21/26586

    摘要： A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

    摘要翻译： 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。