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    Semiconductor device and a method of fabricating the device
    5.
    发明授权
    Semiconductor device and a method of fabricating the device 有权
    半导体装置及其制造方法

    公开(公告)号：US08154107B2

    公开(公告)日：2012-04-10

    申请号：US11703365

    申请日：2007-02-07

    申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L23/58

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.

    摘要翻译： 具有被超应力层覆盖的至少一个晶体管的半导体器件及其制造方法。 在NMOS器件中，超应力层包括源极和漏极区域上的拉伸应力膜，以及多个区域上的压应力膜。 在PMOS器件中，超应力层包括源极和漏极区域上的压缩应力膜和在多个区域上的拉伸应力膜。 在优选实施例中，半导体器件包括PMOS晶体管和形成CMOS器件并被超压应力层覆盖的NMOS晶体管。

    Hybrid Schottky source-drain CMOS for high mobility and low barrier
    6.
    发明授权
    Hybrid Schottky source-drain CMOS for high mobility and low barrier 有权
    用于高移动性和低屏障的混合肖特基源极 - 漏极CMOS

    公开(公告)号：US07737532B2

    公开(公告)日：2010-06-15

    申请号：US11220176

    申请日：2005-09-06

    申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

    发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

    IPC分类号： H01L29/04

    CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

    摘要： A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

    摘要翻译： 提供CMOS器件。 半导体器件包括衬底，衬底具有第一区域和第二区域，第一区域具有由包括{i，j，k}的米勒指数族代表的第一晶体取向，第二区域具有第二晶体取向 表示包括{l，m，n}的米勒指数族，其中l2 + m2 + n2> i2 + j2 + k2。 替代实施例还包括形成在第一区域上的NMOSFET和形成在第二区域上的PMOSFET。 实施例还包括由NMOSFET或PMOSFET中的至少一个形成的肖特基接触。

    BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture
    9.
    发明授权
    BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture 有权
    通过机械单轴应变的BiCMOS性能提高和制造方法

    公开(公告)号：US07466008B2

    公开(公告)日：2008-12-16

    申请号：US11717484

    申请日：2007-03-13

    申请人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    发明人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    IPC分类号： H01L27/06 ,  H01L27/07

    CPC分类号： H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

    摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

    摘要翻译： 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

    CMOS devices with schottky source and drain regions
    10.
    发明申请
    CMOS devices with schottky source and drain regions 审中-公开
    具有肖特基源极和漏极区域的CMOS器件

    公开(公告)号：US20080191285A1

    公开(公告)日：2008-08-14

    申请号：US11704402

    申请日：2007-02-09

    申请人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    发明人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    IPC分类号： H01L29/78 ,  H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

    摘要： A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device are reduced by forming the PMOS device over a semiconductor layer having a low valence band.

    摘要翻译： 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源极/漏极延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。