公开(公告)号：US20110216454A1

公开(公告)日：2011-09-08

申请号：US12719577

申请日：2010-03-08

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yu-Lien Liu ,  Yan-Yu Chen ,  Che-Shih Lin ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yu-Lien Liu ,  Yan-Yu Chen ,  Che-Shih Lin ,  Tao-Cheng Lu

IPC分类号： H02H9/04 ,  H03H11/26

CPC分类号： H02H9/04 ,  H03H11/26

摘要： An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.

摘要翻译： 描述了一种用于提供静电放电（ESD）保护的RC延迟电路。 电路使用NMOS晶体管和PMOS晶体管，使用相对小的电路布局面积产生大的有效电阻。

公开(公告)号：US08345396B2

公开(公告)日：2013-01-01

申请号：US12719577

申请日：2010-03-08

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yu-Lien Liu ,  Yan-Yu Chen ,  Che-Shih Lin ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yu-Lien Liu ,  Yan-Yu Chen ,  Che-Shih Lin ,  Tao-Cheng Lu

IPC分类号： H02H3/22

CPC分类号： H02H9/04 ,  H03H11/26

摘要： An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.

摘要翻译： 描述了一种用于提供静电放电（ESD）保护的RC延迟电路。 电路使用NMOS晶体管和PMOS晶体管，使用相对小的电路布局面积产生大的有效电阻。

公开(公告)号：US08952457B2

公开(公告)日：2015-02-10

申请号：US12181545

申请日：2008-07-29

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L23/62 ,  H01L27/02

CPC分类号： H01L27/0266

摘要： An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate. The first regions are disposed in the substrate and surrounded by the annular well region. The at least one transistor is disposed on the substrate between the first regions and including a source, a gate, and a drain. The annular well region and the drain are coupled to a first voltage source. The source and one of the first regions are coupled to a second voltage source, and the other of the first regions is coupled to a substrate triggering circuit.

摘要翻译： 提供了包括第一导电类型的衬底，第二导电类型的环形阱区域，第一导电类型的两个第一区域和第二导电类型的至少一个晶体管的ESD保护电路。 环形阱区域设置在基板中。 第一区域设置在基板中并被环形区域包围。 至少一个晶体管设置在第一区域之间的衬底上，并且包括源极，栅极和漏极。 环形阱区域和漏极耦合到第一电压源。 源极和第一区域中的一个耦合到第二电压源，并且第一区域中的另一个耦合到衬底触发电路。

公开(公告)号：US20110204447A1

公开(公告)日：2011-08-25

申请号：US12712812

申请日：2010-02-25

申请人： SHIH-YU WANG ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： SHIH-YU WANG ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L27/06

CPC分类号： H01L27/0262

摘要： An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.

摘要翻译： 静电放电容纳装置包括具有第一导电类型的半导体本体和衬垫。 具有第二导电类型的周围阱布置在环中以围绕半导体本体中的静电放电电路的区域。 周围的阱相对较深，除了限定静电放电电路的区域之外，还提供了形成有半导体本体的二极管的第一端子。 在由周围的阱包围的区域内，耦合到焊盘的二极管和耦合到电压基准的晶体管串联连接并在半导体本体中形成寄生器件。

公开(公告)号：US20100109043A1

公开(公告)日：2010-05-06

申请号：US12410335

申请日：2009-03-24

申请人： SHIH-YU WANG ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： SHIH-YU WANG ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/73

CPC分类号： H01L29/7436 ,  H01L27/0251 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H03K17/08 ,  H03K19/003 ,  H01L2924/00

摘要： A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.

摘要翻译： 半导体器件包括第一导电类型的第一阱区域，第二导电类型的第二阱区域，第一阱区域内的第二导电类型的源极区域和至少部分地在第二阱区域内的第二导电类型的漏极区域 第二个井区。 与第一阱区的良好接触耦合到源。 第一导电类型的第三掺杂区域和第二导电类型的第四掺杂区域位于第二阱区域中。 第一晶体管包括第三掺杂区域，第二阱区域和第一阱区域。 第一晶体管耦合到开关器件。 第二晶体管包括第二阱区，第一阱区和源极区。 第一和第二晶体管被配置为在ESD事件期间提供电流路径。

公开(公告)号：US09153570B2

公开(公告)日：2015-10-06

申请号：US12712812

申请日：2010-02-25

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L23/62 ,  H01L27/02

CPC分类号： H01L27/0262

摘要： An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.

摘要翻译： 静电放电容纳装置包括具有第一导电类型的半导体本体和衬垫。 具有第二导电类型的周围阱布置在环中以围绕半导体本体中的静电放电电路的区域。 周围的阱相对较深，除了限定静电放电电路的区域之外，还提供了形成有半导体本体的二极管的第一端子。 在由周围的阱包围的区域内，耦合到焊盘的二极管和耦合到电压基准的晶体管串联连接并在半导体本体中形成寄生器件。

公开(公告)号：US08748936B2

公开(公告)日：2014-06-10

申请号：US13555075

申请日：2012-07-20

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/73

CPC分类号： H01L29/7436 ,  H01L27/0251 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H03K17/08 ,  H03K19/003 ,  H01L2924/00

摘要： A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region.

摘要翻译： 半导体器件包括第一导电类型的第一阱区域和第一阱区域内的第二导电类型的第二阱区域。 第一导电类型的第一区域和第二导电类型的第二区域设置在第二阱区域内。 第一导电类型的第三区域和第二导电类型的第四区域设置在第一阱区域内，其中第三区域和第四区域被第二阱区域分开。 半导体器件还包括耦合到第三区域的开关器件。

公开(公告)号：US20090273033A1

公开(公告)日：2009-11-05

申请号：US12181545

申请日：2008-07-29

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/00

CPC分类号： H01L27/0266

摘要： An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate. The first regions are disposed in the substrate and surrounded by the annular well region. The at least one transistor is disposed on the substrate between the first regions and including a source, a gate, and a drain. The annular well region and the drain are coupled to a first voltage source. The source and one of the first regions are coupled to a second voltage source, and the other of the first regions is coupled to a substrate triggering circuit.

摘要翻译： 提供了包括第一导电类型的衬底，第二导电类型的环形阱区域，第一导电类型的两个第一区域和第二导电类型的至少一个晶体管的ESD保护电路。 环形阱区域设置在基板中。 第一区域设置在基板中并被环形区域包围。 至少一个晶体管设置在第一区域之间的衬底上，并且包括源极，栅极和漏极。 环形阱区域和漏极耦合到第一电压源。 源极和第一区域中的一个耦合到第二电压源，并且第一区域中的另一个耦合到衬底触发电路。

公开(公告)号：US20120286322A1

公开(公告)日：2012-11-15

申请号：US13555075

申请日：2012-07-20

申请人： SHIH-YU WANG ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： SHIH-YU WANG ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/73

CPC分类号： H01L29/7436 ,  H01L27/0251 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H03K17/08 ,  H03K19/003 ,  H01L2924/00

摘要： A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region.

摘要翻译： 半导体器件包括第一导电类型的第一阱区域和第一阱区域内的第二导电类型的第二阱区域。 第一导电类型的第一区域和第二导电类型的第二区域设置在第二阱区域内。 第一导电类型的第三区域和第二导电类型的第四区域设置在第一阱区域内，其中第三区域和第四区域被第二阱区域分开。 半导体器件还包括耦合到第三区域的开关器件。

公开(公告)号：US08253165B2

公开(公告)日：2012-08-28

申请号：US12410335

申请日：2009-03-24

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yan-Yu Chen ,  Yu-Lien Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/74 ,  H01L23/62

CPC分类号： H01L29/7436 ,  H01L27/0251 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H03K17/08 ,  H03K19/003 ,  H01L2924/00

摘要： A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.

摘要翻译： 半导体器件包括第一导电类型的第一阱区域，第二导电类型的第二阱区域，第一阱区域内的第二导电类型的源极区域和至少部分地在第二阱区域内的第二导电类型的漏极区域 第二个井区。 与第一阱区的良好接触耦合到源。 第一导电类型的第三掺杂区域和第二导电类型的第四掺杂区域位于第二阱区域中。 第一晶体管包括第三掺杂区域，第二阱区域和第一阱区域。 第一晶体管耦合到开关器件。 第二晶体管包括第二阱区，第一阱区和源极区。 第一和第二晶体管被配置为在ESD事件期间提供电流路径。