公开(公告)号：US5825773A

公开(公告)日：1998-10-20

申请号：US853242

申请日：1992-03-18

申请人： Shin'ichi Shutoh ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

发明人： Shin'ichi Shutoh ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

IPC分类号： G06F15/173 ,  H04L12/18 ,  H04L12/931 ,  G06F13/00

CPC分类号： G06F15/17393 ,  H04L49/201 ,  H04L49/205

摘要： In a method of transferring packets in a network for a parallel processor system handling a one-to-one transfer packet to be transferred from a processor to another processor and a broadcast packet to be transferred from a processor to a plurality of other processors, a transfer request of a broadcast packet is preferentially selected and a check is made to detect whether or not a plurality of processors specified as receivers are in a state in which the packet can be received. The broadcast packet is transferred to the processors found to be in the state in which the packet can be received. The packet transfer is delayed for the other processors in a state in which the packet cannot be received. Namely, only when the state of the processors is changed to the state in which the packet can be received, the broadcast packet is transferred thereto.

摘要翻译： 在用于处理要从处理器传送到另一处理器的一对一传送分组的并行处理器系统的网络中传送分组的方法以及要从处理器传送到多个其他处理器的广播分组的方法中， 优先选择广播分组的传送请求，并进行检查，以检测指定为接收者的多个处理器是否处于可以接收分组的状态。 广播分组被传送到发现处于可以接收分组的状态的处理器。 在其中不能接收分组的状态下，其他处理器的分组传送被延迟。 也就是说，只有当处理器的状态改变为可以接收分组的状态时，广播分组被传送到其中。

公开(公告)号：US5386566A

公开(公告)日：1995-01-31

申请号：US853427

申请日：1992-03-18

申请人： Naoki Hamanaka ,  Junji Nakagoshi ,  Tatsuo Higuchi ,  Hiroyuki Chiba ,  Shin'ichi Shutoh ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

发明人： Naoki Hamanaka ,  Junji Nakagoshi ,  Tatsuo Higuchi ,  Hiroyuki Chiba ,  Shin'ichi Shutoh ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

IPC分类号： G06F9/46 ,  H04L29/00 ,  G06F13/00

CPC分类号： G06F9/544 ,  H04L29/00

摘要： In a parallel computer, in order to reduce the overhead of data transmissions between the processes, a data transmission from the virtual space of a process in a certain cluster to the virtual space of a process in other cluster is executed without copying the data to the buffer provided within the operating system. The real communication area resident in the real memory is provided in a part of the virtual space of the process, and an identifier unique within the cluster is given to the communication area. When the transmission process has issued a transmission instruction at the time of data transmission, the cluster address of the cluster in which the transmission destination process exists and the identifier of the communication area are determined based on the name of the transmission destination process. Then, the data is directly transmitted between the mutual real communication areas of the transmission originating process and the transmission destination process. Overhead for the data transmission between the processes can be reduced by avoiding making a copy of the data between the user space and the buffer provided within the operating system at the time of data transmission between the processes.

摘要翻译： 在并行计算机中，为了减少进程之间的数据传输的开销，执行从某个群集中的进程的虚拟空间到其他群集中的进程的虚拟空间的数据传输，而不将数据复制到 在操作系统中提供缓冲区。 驻留在真实存储器中的实际通信区域被提供在该进程的虚拟空间的一部分中，并且在群集内唯一的标识符被提供给通信区域。 当发送处理在数据发送时发出发送指示时，基于发送目的地处理的名称确定发送目的地处理所在的群集的群集地址和通信区域的标识符。 然后，数据在发送始发处理的相互实际通信区域和发送目的地处理之间直接发送。 可以通过在进程之间的数据传输时避免在用户空间和在操作系统内提供的缓冲区之间的数据的副本来复制用于进程之间的数据传输的开销。

公开(公告)号：US5826049A

公开(公告)日：1998-10-20

申请号：US916630

申请日：1992-07-22

申请人： Yasuhiro Ogata ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Taturu Toba ,  Teruo Tanaka

发明人： Yasuhiro Ogata ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Taturu Toba ,  Teruo Tanaka

IPC分类号： G06F15/173 ,  G06F15/80 ,  G06F15/163

CPC分类号： G06F15/17368

摘要： In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.

摘要翻译： 为了确定消息到接收端处理器组的传送路径，处理器包括路由位生成电路，并且交换交换机包括部分广播路径控制电路和路径控制信息改变电路。 为了定义接收端处理器组的范围，网络包括传送控制电路。 交叉开关包括与输出端口和边界寄存器组相关联的传输控制电路。 当在输出端口的下游方向上从输入端口传送部分广播消息时，确定属于与连接到特定输入端口的连接的部分广播范围是否连接到特定输出端口，由此 特定的部分广播消息从相同的输出端口传送。

公开(公告)号：US5377333A

公开(公告)日：1994-12-27

申请号：US945483

申请日：1992-09-15

申请人： Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shinichi Shutoh ,  Yasuhiro Ogata ,  Shigeo Takeuchi ,  Tatsuru Toba

发明人： Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shinichi Shutoh ,  Yasuhiro Ogata ,  Shigeo Takeuchi ,  Tatsuru Toba

IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17375

摘要： Crossbar switches having 2.sup.n +1 ports and computing clusters are arranged so that each crossbar switch is connected to 2.sup.n processors. Auxiliary processors that perform parallel processing administrative functions and input/output functions are arranged at the remainder ports of the crossbar switches. Exchangers are provided to connect each processor and its crossbar switches. Parallel processing may be executed by the 2.sup.n processors independently of processing by the auxiliary processors for speed. One mounting unit is formed of a crossbar switch of one dimension, the processor group connected to that crossbar switch, and all of the crossbar switches of a different dimension that are connected to one of the processors of the one processor group. The parallel processor system is mounted by just combining mounting units with no need for special LSIs or frames or the like on which to mount the crossbar switches and without the interfaces that connect the processor and the network becoming concentrated in one place.

摘要翻译： 具有2n + 1个端口和计算集群的交叉开关被布置成使得每个交叉开关连接到2n个处理器。 执行并行处理管理功能和输入/输出功能的辅助处理器被布置在交叉开关的其余端口处。 提供交换器来连接每个处理器及其交叉开关。 独立于辅助处理器对速度的处理，可以由2n个处理器执行并行处理。 一个安装单元由一维的交叉开关构成，处理器组连接到该交叉开关，以及连接到一个处理器组的一个处理器的不同维度的所有交叉开关。 并行处理器系统仅通过组合安装单元来安装，不需要特殊的LSI或框架等，在其上安装交叉开关，并且没有连接处理器和网络的接口变得集中在一个地方。

公开(公告)号：US5758053A

公开(公告)日：1998-05-26

申请号：US189683

申请日：1994-02-01

申请人： Shigeo Takeuchi ,  Yasuhiro Inagaki ,  Junji Nakagoshi ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Hiroaki Fujii ,  Yoshiko Yasuda ,  Kiyohiro Obara ,  Taturu Toba ,  Masahiro Yamada

发明人： Shigeo Takeuchi ,  Yasuhiro Inagaki ,  Junji Nakagoshi ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Hiroaki Fujii ,  Yoshiko Yasuda ,  Kiyohiro Obara ,  Taturu Toba ,  Masahiro Yamada

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  H04J6/00 ,  H04L12/00

CPC分类号： G06F11/1443 ,  G06F11/0724 ,  G06F11/0784 ,  G06F11/10

摘要： Parallel processors communicate with each other over a network by transmitting messages that include destination processor information. A message controller for each processor in the network receives the messages and checks for faults in the message, particularly in the destination processor number contained in a first word of the message. If a fault occurs in the destination processor number, then the faulty message is transmitted to an appropriate processor for handling the fault. In this way the network operation is not suspended because of the fault and the message is not left in the network as a result of the error occurring in the destination processor number. The processor to which the faulty message is directed is determined by a substitute destination processor number contained in the message or is predetermined and set in another way, such as by a service processor. To recover from the fault, the processor receiving the faulty message can request that the message be retransmitted or the error can be corrected using an ECC, for example. If the faulty message cannot be retransmitted, then the processor or the host processor can request that the job to which the faulty message pertains be canceled by all of the processors executing that job without affecting the simultaneous execution of other jobs by the same processors.

摘要翻译： 并行处理器通过发送包含目标处理器信息的消息通过网络彼此进行通信。 用于网络中的每个处理器的消息控制器接收消息并检查消息中的故障，特别是在消息的第一个字中包含的目标处理器号码中。 如果目标处理器号码发生故障，则故障消息被传送到适当的处理器处理故障。 以这种方式，网络操作由于故障而不被暂停，并且由于目标处理器号码中出现错误，网络中没有留下该消息。 错误消息所针对的处理器由包含在消息中的替代目的地处理器号码确定，或者以另一种方式例如由服务处理器预先设定。 为了从故障中恢复，例如，接收到故障消息的处理器可以请求重传该消息或者使用ECC来纠正该错误。 如果故障消息不能重发，则处理器或主机处理器可以请求执行该作业的所有处理器取消与故障消息相关的作业，而不会影响同一处理器同时执行其他作业。

公开(公告)号：US5822605A

公开(公告)日：1998-10-13

申请号：US408561

申请日：1995-03-22

申请人： Tatsuo Higuchi ,  Tadaaki Isobe ,  Junji Nakagoshi ,  Shigeo Takeuchi ,  Tatsuru Toba ,  Yoshiko Yasuda ,  Teruo Tanaka ,  Takayuki Nakagawa ,  Yuji Saeki

发明人： Tatsuo Higuchi ,  Tadaaki Isobe ,  Junji Nakagoshi ,  Shigeo Takeuchi ,  Tatsuru Toba ,  Yoshiko Yasuda ,  Teruo Tanaka ,  Takayuki Nakagawa ,  Yuji Saeki

IPC分类号： G06F15/173 ,  H04L12/56 ,  G06F13/00 ,  H04L12/50

CPC分类号： H04L45/06 ,  G06F15/17381

摘要： In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks. These schemes all apply where long messages are transmitted through worm-hole routing.

摘要翻译： 在包括构成网络的多个处理器元件的并行处理器系统中，希望向多个目的地处理器元件广播数据的源处理器元件向广播交换机发送包含目标数据的广播请求消息。 广播交换机将接收的消息转换成广播消息，并通过网络将其发送到目的地。 如果与广播交换机并行发送的多个广播请求消息被序列化，从而在网络上一次只能发送一个广播消息。 这可以防止不同广播消息之间发生死锁。 用于发送广播请求消息的路由和用于发送广播消息的路由被布置为不彼此重叠。 这抑制了任何广播请求消息和广播消息之间的死锁。 广播交换机被替换为部分网络之一。 这些方案都适用于通过蠕虫孔路由传输长消息的情况。

公开(公告)号：US06038607A

公开(公告)日：2000-03-14

申请号：US407841

申请日：1995-03-21

申请人： Patrick Hamilton ,  Junji Nakagoshi ,  Tatsuo Higuchi ,  Toshimitsu Ando ,  Masaaki Iwasaki

发明人： Patrick Hamilton ,  Junji Nakagoshi ,  Tatsuo Higuchi ,  Toshimitsu Ando ,  Masaaki Iwasaki

IPC分类号： G06F13/24 ,  G06F15/17 ,  G06F15/16 ,  G06F9/46

CPC分类号： G06F15/17 ,  G06F13/24

摘要： To reduce an overhead of the interrupt on a processor associated with packet send and receive control in a network, a packet send command chaining unit is provided. Based on the control field in each packet send command, a send node controls an interrupt request to the processor in the packet level and sends a packet set with the control information to a receive node. Based on the control field in the received data packet, the receive node controls a receive circuit interrupt request, thereby reducing the number of times the interrupt on the instruction processor is caused for each packet send and receive operation.

摘要翻译： 为了减少与网络中的分组发送和接收控制相关联的处理器上的中断的开销，提供了分组发送命令链接单元。 基于每个分组发送命令中的控制字段，发送节点控制分组级别中的处理器的中断请求，并将具有控制信息的分组发送到接收节点。 基于接收到的数据包中的控制字段，接收节点控制接收电路中断请求，从而减少每个包发送和接收操作引起指令处理器中断的次数。

公开(公告)号：US5594868A

公开(公告)日：1997-01-14

申请号：US407853

申请日：1995-03-21

申请人： Junji Nakagoshi ,  Tatsuo Higuchi ,  Shinichi Kato ,  Toshimitsu Ando ,  Masaaki Iwasaki

发明人： Junji Nakagoshi ,  Tatsuo Higuchi ,  Shinichi Kato ,  Toshimitsu Ando ,  Masaaki Iwasaki

IPC分类号： G06F12/14 ,  G06F15/173 ,  G06F13/14 ,  G06F15/16 ,  G06F15/163

CPC分类号： G06F15/17368

摘要： A parallel processor system includes: a reception buffer pointer controller for generating an address of a reception buffer area in which a received packet is written and for checking whether there is no space area in the reception buffer area; a discard command bit capable of being set and reset by an instruction processor; a received packet discard judging unit for judging from the discard command bit and information supplied from the reception buffer pointer controller, whether the received packet is written, suspended, or discarded; and a reception controller for controlling to write the received packet in the reception buffer area in accordance with an judgement by the received packet discard judging unit. With this arrangement, even if there is no space area in the reception buffer area for storing a received packet or even if the received packet cannot be received because of a failure in the reception processor unit, the received packet can be discarded at the reception processor unit.

摘要翻译： 并行处理器系统包括：接收缓冲器指针控制器，用于产生其中写入接收到的分组的接收缓冲器区域的地址，并且用于检查接收缓冲区域中是否没有空间区域; 能够由指令处理器设置和复位的丢弃命令位; 接收到的分组丢弃判断单元，用于从丢弃命令比特和从接收缓冲器指针控制器提供的信息判断所接收的分组是否被写入，暂停或丢弃; 以及接收控制器，用于根据接收到的分组丢弃判断单元的判断，控制将接收到的分组写入接收缓冲区。 利用这种布置，即使接收缓冲区中没有用于存储接收到的分组的空间区域，或者即使接收到的分组由于接收处理单元的故障而不能接收，也可以在接收处理器中丢弃所接收的分组 单元。

公开(公告)号：US20060288348A1

公开(公告)日：2006-12-21

申请号：US11485273

申请日：2006-07-13

申请人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Naoki Hamanaka

发明人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Naoki Hamanaka

IPC分类号： G06F9/46

CPC分类号： G06F9/5077 ,  G06F9/5083

摘要： Disclosed are a virtual computer system and method, wherein computer resources are automatically and optimally allocated to logical partitions according to loads to be accomplished by operating systems in the logical partitions and setting information based on a knowledge of workloads that run on the operating systems. Load measuring modules are installed on the operating systems in order to measure the loads to be accomplished by the operating systems. A manager designates the knowledge concerning the workloads on the operating systems through a user interface. An adaptive control module determines the allocation rations of the computer resources relative to the logical partitions according to the loads and the settings, and issues an allocation varying instruction to a hypervisor so as to thus instruct variation of allocations.

公开(公告)号：US06757788B2

公开(公告)日：2004-06-29

申请号：US09941834

申请日：2001-08-30

申请人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Hiromitsu Maeda ,  Naoki Hamanaka

发明人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Hiromitsu Maeda ,  Naoki Hamanaka

IPC分类号： G06F1300

CPC分类号： G06F12/0817 ,  G06F12/0815

摘要： A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an extended node larger than a block size of the internal cache of a CPU. When a memory access is performed, the access right memory is referred to, and if the node has an access right to the extended block including a target block, the block is accessed without cache coherence control at other nodes.

摘要翻译： 一种用于具有由网络互连的多个CPU节点，存储器节点和I / O节点的多CPU系统的高速缓存一致性控制系统。 每个CPU节点控制电路具有访问权限存储器，用于以比CPU的内部高速缓存的块大小更大的扩展节点来管理节点的访问权限。 当执行存储器访问时，参考访问权限存储器，并且如果节点对包括目标块的扩展块具有访问权限，则在其他节点处访问该块而不进行高速缓存一致性控制。