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公开(公告)号：US08298935B2
公开(公告)日：2012-10-30
申请号：US12952179
申请日：2010-11-22
IPC分类号： H01L21/4763
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811
摘要： A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
摘要翻译： 公开了一种双镶嵌工艺。 该方法包括以下步骤：在基底上形成电介质层; 在所述电介质层上形成第一图案化掩模，其中所述第一图案化掩模包括开口; 在所述电介质层上形成材料层并覆盖所述第一图案化掩模; 在所述电介质层上形成第二图案化掩模，其中所述第二图案化掩模包括第一孔; 在所述第二图案化掩模中形成第二孔，其中所述第二孔和所述第一孔包括它们之间的间隙; 并且利用第二图案化掩模作为蚀刻掩模，用于通过第一孔和第二孔部分去除材料层和介电层。
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公开(公告)号：US10199232B2
公开(公告)日：2019-02-05
申请号：US13033696
申请日：2011-02-24
申请人： Shin-Chi Chen , Jiunn-Hsiung Liao , Yu-Tsung Lai
发明人： Shin-Chi Chen , Jiunn-Hsiung Liao , Yu-Tsung Lai
IPC分类号： H01L29/49 , H01L21/311 , H01L21/768
摘要： Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.
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公开(公告)号：US08791013B2
公开(公告)日：2014-07-29
申请号：US13568137
申请日：2012-08-07
IPC分类号： H01L21/4763
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811
摘要： A pattern forming method is disclosed. The method includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the material layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask after forming the first aperture, wherein the second aperture and the first aperture comprise a gap therebetween and overlap the opening; and utilizing the second patterned mask as an etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
摘要翻译： 公开了图案形成方法。 该方法包括以下步骤：在基底上形成电介质层; 在所述电介质层上形成第一图案化掩模，其中所述第一图案化掩模包括开口; 在所述电介质层上形成材料层并覆盖所述第一图案化掩模; 在所述材料层上形成第二图案化掩模，其中所述第二图案化掩模包括第一孔; 在形成所述第一孔之后在所述第二图案化掩模中形成第二孔，其中所述第二孔和所述第一孔包括它们之间的间隙并与所述开口重叠; 并且利用第二图案化掩模作为蚀刻掩模，用于通过第一孔和第二孔部分去除材料层和介电层。
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公开(公告)号：US20120129337A1
公开(公告)日：2012-05-24
申请号：US12952179
申请日：2010-11-22
IPC分类号： H01L21/768
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811
摘要： A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
摘要翻译： 公开了一种双镶嵌工艺。 该方法包括以下步骤：在基底上形成电介质层; 在所述电介质层上形成第一图案化掩模，其中所述第一图案化掩模包括开口; 在所述电介质层上形成材料层并覆盖所述第一图案化掩模; 在所述电介质层上形成第二图案化掩模，其中所述第二图案化掩模包括第一孔; 在所述第二图案化掩模中形成第二孔，其中所述第二孔和所述第一孔包括它们之间的间隙; 并且利用第二图案化掩模作为蚀刻掩模，用于通过第一孔和第二孔部分去除材料层和介电层。
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公开(公告)号：US20120302056A1
公开(公告)日：2012-11-29
申请号：US13568137
申请日：2012-08-07
IPC分类号： H01L21/768
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811
摘要： A pattern forming method is disclosed. The method includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the material layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask after forming the first aperture, wherein the second aperture and the first aperture comprise a gap therebetween and overlap the opening; and utilizing the second patterned mask as an etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
摘要翻译： 公开了图案形成方法。 该方法包括以下步骤：在基底上形成电介质层; 在所述电介质层上形成第一图案化掩模，其中所述第一图案化掩模包括开口; 在所述电介质层上形成材料层并覆盖所述第一图案化掩模; 在所述材料层上形成第二图案化掩模，其中所述第二图案化掩模包括第一孔; 在形成所述第一孔之后在所述第二图案化掩模中形成第二孔，其中所述第二孔和所述第一孔包括它们之间的间隙并与所述开口重叠; 并且利用第二图案化掩模作为蚀刻掩模，用于通过第一孔和第二孔部分去除材料层和电介质层。
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公开(公告)号：US20120217552A1
公开(公告)日：2012-08-30
申请号：US13033696
申请日：2011-02-24
申请人： Shin-Chi Chen , Jiunn-Hsiung Liao , Yu-Tsung Lai
发明人： Shin-Chi Chen , Jiunn-Hsiung Liao , Yu-Tsung Lai
IPC分类号： H01L21/336 , H01L21/28 , H01L23/48
CPC分类号： H01L21/31144 , H01L21/76816
摘要： Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.
摘要翻译： 提供示例性金属线结构和沟槽的制造方法。 特别地，金属线结构包括基板，目标层，沟槽和导体线。 目标层形成在基板上。 沟槽形成在目标层中，并且在其底部形成微沟槽。 微沟的深度不超过50埃。 导体线嵌入沟槽。
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公开(公告)号：US08323877B2
公开(公告)日：2012-12-04
申请号：US12947139
申请日：2010-11-16
申请人： Ming-Da Hsieh , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Ming-Da Hsieh , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： G03F7/26
CPC分类号： H01L21/76811 , G03F7/094 , H01L21/31138 , H01L21/31144 , H01L21/76802
摘要： A patterning method and a method for fabricating a dual damascene opening are described, wherein the patterning method includes following steps. An organic layer, a silicon-containing mask layer and a patterned photoresist layer are formed on a material layer in sequence. The silicon-containing mask layer is removed using the patterned photoresist layer as a mask. A reactive gas is used for conducting an etching step so as to remove the organic layer with the silicon-containing mask layer as a mask, wherein the reactive gas contains no oxygen species. The material layer is removed using the organic layer as a mask, so that an opening is formed in the material layer. The organic layer is then removed.
摘要翻译： 描述了用于制造双镶嵌开口的图案化方法和方法，其中图案化方法包括以下步骤。 在材料层上依次形成有机层，含硅掩模层和图案化的光致抗蚀剂层。 使用图案化的光致抗蚀剂层作为掩模去除含硅掩模层。 使用反应性气体进行蚀刻步骤，以便以含硅掩模层作为掩模去除有机层，其中反应气体不含氧物质。 使用有机层作为掩模去除材料层，从而在材料层中形成开口。 然后除去有机层。
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公开(公告)号：US20120122035A1
公开(公告)日：2012-05-17
申请号：US12947139
申请日：2010-11-16
申请人： MING-DA HSIEH , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： MING-DA HSIEH , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： G03F7/20
CPC分类号： H01L21/76811 , G03F7/094 , H01L21/31138 , H01L21/31144 , H01L21/76802
摘要： A patterning method and a method for fabricating a dual damascene opening are described, wherein the patterning method includes following steps. An organic layer, a silicon-containing mask layer and a patterned photoresist layer are formed on a material layer in sequence. The silicon-containing mask layer is removed using the patterned photoresist layer as a mask. A reactive gas is used for conducting an etching step so as to remove the organic layer with the silicon-containing mask layer as a mask, wherein the reactive gas contains no oxygen species. The material layer is removed using the organic layer as a mask, so that an opening is formed in the material layer. The organic layer is then removed.
摘要翻译： 描述了用于制造双镶嵌开口的图案化方法和方法，其中图案化方法包括以下步骤。 在材料层上依次形成有机层，含硅掩模层和图案化的光致抗蚀剂层。 使用图案化的光致抗蚀剂层作为掩模去除含硅掩模层。 使用反应性气体进行蚀刻步骤，以便以含硅掩模层作为掩模去除有机层，其中反应气体不含氧物质。 使用有机层作为掩模去除材料层，从而在材料层中形成开口。 然后除去有机层。
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公开(公告)号：US20100105205A1
公开(公告)日：2010-04-29
申请号：US12259033
申请日：2008-10-27
申请人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/3281 , H01L21/02063 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water.
摘要翻译： 提供半导体工艺。 首先，在基板上依次形成金属层，电介质层和图案化的硬掩模层。 此后，去除介电层的一部分以形成露出金属层的开口。 之后，使用清洁溶液清洁开口。 清洗液含有含量为0.00275〜3重量％的三唑化合物，含量为1〜10重量％的硫酸，含量为1〜200ppm的氢氟酸和水。
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公开(公告)号：US20080171433A1
公开(公告)日：2008-07-17
申请号：US11621996
申请日：2007-01-11
IPC分类号： H01L21/768
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF 4 N 3 N 3等离子体从双镶嵌开口选择性地去除暴露的盖层。
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