公开(公告)号：US07173451B2

公开(公告)日：2007-02-06

申请号：US11081589

申请日：2005-03-17

申请人： Shinichi Kanno ,  Masaya Tarui ,  Taku Ohneda ,  Riku Ogawa

发明人： Shinichi Kanno ,  Masaya Tarui ,  Taku Ohneda ,  Riku Ogawa

IPC分类号： H03K19/173

CPC分类号： H03K19/17752

摘要： A programmable logic circuit apparatus includes a programmable logic circuit that dynamically switches and operates a plurality of circuit blocks. The circuit blocks include a branch circuit block that performs branch processing and a plurality of child circuit blocks that selectively perform a plurality of kinds of processing on data obtained by the branch circuit block. The apparatus also includes a storage unit that stores data obtained by the branch circuit block and an identifier of a child circuit block into which the data is input. The identifier is associated with the data. The apparatus also includes a controller that causes the programmable logic circuit to process data associated with the same identifier as an identifier of a child circuit block being in operation in the programmable logic circuit, among the data stored in the storage unit, in preference to data associated with identifiers of other child circuit blocks.

摘要翻译： 可编程逻辑电路装置包括动态地切换和操作多个电路块的可编程逻辑电路。 电路块包括执行分支处理的分支电路块和对由分支电路块获得的数据选择性地执行多种处理的多个子电路块。 该装置还包括存储单元，其存储由分支电路块获得的数据和输入数据的子电路块的标识符。 标识符与数据相关联。 该装置还包括一个控制器，该控制器使可编程逻辑电路处理与存储在存储单元中的数据相对应的与可编程逻辑电路中正在操作的子电路块的标识符相同的标识符的数据，优先于数据 与其他子电路块的标识符相关联。

公开(公告)号：US20060017459A1

公开(公告)日：2006-01-26

申请号：US11081589

申请日：2005-03-17

申请人： Shinichi Kanno ,  Masaya Tarui ,  Taku Ohneda ,  Riku Ogawa

发明人： Shinichi Kanno ,  Masaya Tarui ,  Taku Ohneda ,  Riku Ogawa

IPC分类号： H03K19/177

CPC分类号： H03K19/17752

摘要： A programmable logic circuit apparatus includes a programmable logic circuit that dynamically switches and operates a plurality of circuit blocks. The circuit blocks include a branch circuit block that performs branch processing and a plurality of child circuit blocks that selectively perform a plurality of kinds of processing on data obtained by the branch circuit block. The apparatus also includes a storage unit that stores data obtained by the branch circuit block and an identifier of a child circuit block into which the data is input. The identifier is associated with the data. The apparatus also includes a controller that causes the programmable logic circuit to process data associated with the same identifier as an identifier of a child circuit block being in operation in the programmable logic circuit, among the data stored in the storage unit, in preference to data associated with identifiers of other child circuit blocks.

摘要翻译： 可编程逻辑电路装置包括动态地切换和操作多个电路块的可编程逻辑电路。 电路块包括执行分支处理的分支电路块和对由分支电路块获得的数据选择性地执行多种处理的多个子电路块。 该装置还包括存储单元，其存储由分支电路块获得的数据和输入数据的子电路块的标识符。 标识符与数据相关联。 该装置还包括一个控制器，该控制器使可编程逻辑电路处理与存储在存储单元中的数据相当的与可编程逻辑电路中正在操作的子电路块的标识符相同的标识符的数据，优先于数据 与其他子电路块的标识符相关联。

公开(公告)号：US20050268125A1

公开(公告)日：2005-12-01

申请号：US11128187

申请日：2005-05-13

申请人： Taku Ohneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

发明人： Taku Ohneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

IPC分类号： G06F1/32 ,  G06F1/08 ,  G06F1/30 ,  H03K19/00 ,  H03K19/173

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Programmable logic circuits are changeable circuit components based on circuit data. A circuit data memory stores a plurality of circuit data and performance requirements. A feature data memory stores feature data of each programmable logic circuit. A control unit calculates a minimum voltage of the plurality of programmable logic circuits to execute the plurality of circuit data based on the performance requirements, and selectively assigns the plurality of circuit data to the plurality of programmable logic circuits so that the performance requirement of circuit data assigned to each programmable logic circuit is within the operation range of the programmable logic circuit at the minimum voltage. A supply unit supplies the minimum voltage to the plurality of programmable logic circuits.

摘要翻译： 可编程逻辑电路是基于电路数据的可变电路组件。 电路数据存储器存储多个电路数据和性能要求。 特征数据存储器存储每个可编程逻辑电路的特征数据。 控制单元基于性能要求，计算多个可编程逻辑电路的最小电压，以执行多个电路数据，并且选择性地将多个电路数据分配给多个可编程逻辑电路，使得电路数据的性能要求 分配给每个可编程逻辑电路的可编程逻辑电路在最小电压范围内。 供电单元向多个可编程逻辑电路提供最小电压。

公开(公告)号：US07533282B2

公开(公告)日：2009-05-12

申请号：US11949072

申请日：2007-12-03

申请人： Taku Ohneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

发明人： Taku Ohneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory is used to store a plurality of circuit data and performance requirements for the circuit data. The control unit is configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits so that a total power of all programmable logic circuits minimizes on condition that the performance requirement of the circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.

摘要翻译： 逻辑电路装置包括多个可编程逻辑电路，电路数据存储器，控制单元。 多个可编程逻辑电路各自被配置为具有基于电路数据的可变电路部件。 每个可编程逻辑电路具有不同的处理性能。 电路数据存储器用于存储电路数据的多个电路数据和性能要求。 控制单元被配置为选择性地将多个电路数据分配给多个可编程逻辑电路，使得所有可编程逻辑电路的总功率在分配给每个可编程逻辑电路的电路数据的性能要求在 处理每个可编程逻辑电路的性能。

公开(公告)号：US07386741B2

公开(公告)日：2008-06-10

申请号：US11128187

申请日：2005-05-13

申请人： Taku Ohneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

发明人： Taku Ohneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

IPC分类号： G06F1/00 ,  G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Programmable logic circuits are changeable circuit components based on circuit data. A circuit data memory stores a plurality of circuit data and performance requirements. A feature data memory stores feature data of each programmable logic circuit. A control unit calculates a minimum voltage of the plurality of programmable logic circuits to execute the plurality of circuit data based on the performance requirements, and selectively assigns the plurality of circuit data to the plurality of programmable logic circuits so that the performance requirement of circuit data assigned to each programmable logic circuit is within the operation range of the programmable logic circuit at the minimum voltage. A supply unit supplies the minimum voltage to the plurality of programmable logic circuits.

摘要翻译： 可编程逻辑电路是基于电路数据的可变电路组件。 电路数据存储器存储多个电路数据和性能要求。 特征数据存储器存储每个可编程逻辑电路的特征数据。 控制单元基于性能要求，计算多个可编程逻辑电路的最小电压，以执行多个电路数据，并且选择性地将多个电路数据分配给多个可编程逻辑电路，使得电路数据的性能要求 分配给每个可编程逻辑电路的可编程逻辑电路的工作范围内处于最小电压。 供电单元向多个可编程逻辑电路提供最小电压。

公开(公告)号：US20080100338A1

公开(公告)日：2008-05-01

申请号：US11949072

申请日：2007-12-03

申请人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

发明人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

IPC分类号： H03K19/177

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory is used to store a plurality of circuit data and performance requirements for the circuit data. The control unit is configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits so that a total power of all programmable logic circuits minimizes on condition that the performance requirement of the circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.

摘要翻译： 逻辑电路装置包括多个可编程逻辑电路，电路数据存储器，控制单元。 多个可编程逻辑电路各自被配置为具有基于电路数据的可变电路部件。 每个可编程逻辑电路具有不同的处理性能。 电路数据存储器用于存储电路数据的多个电路数据和性能要求。 控制单元被配置为选择性地将多个电路数据分配给多个可编程逻辑电路，使得所有可编程逻辑电路的总功率在分配给每个可编程逻辑电路的电路数据的性能要求在 处理每个可编程逻辑电路的性能。