公开(公告)号：US20080100338A1

公开(公告)日：2008-05-01

申请号：US11949072

申请日：2007-12-03

申请人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

发明人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

IPC分类号： H03K19/177

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory is used to store a plurality of circuit data and performance requirements for the circuit data. The control unit is configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits so that a total power of all programmable logic circuits minimizes on condition that the performance requirement of the circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.

摘要翻译： 逻辑电路装置包括多个可编程逻辑电路，电路数据存储器，控制单元。 多个可编程逻辑电路各自被配置为具有基于电路数据的可变电路部件。 每个可编程逻辑电路具有不同的处理性能。 电路数据存储器用于存储电路数据的多个电路数据和性能要求。 控制单元被配置为选择性地将多个电路数据分配给多个可编程逻辑电路，使得所有可编程逻辑电路的总功率在分配给每个可编程逻辑电路的电路数据的性能要求在 处理每个可编程逻辑电路的性能。

公开(公告)号：US20050138445A1

公开(公告)日：2005-06-23

申请号：US10960707

申请日：2004-10-08

申请人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto

发明人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto

IPC分类号： H01L21/822 ,  G06F1/26 ,  G06F1/32 ,  H01L21/82 ,  H01L27/04 ,  H03K19/00 ,  H03K19/173

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3296 ,  H03K19/0008 ,  H03K19/0016 ,  H03K19/1736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17784 ,  H03K19/17788 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.

摘要翻译： 通过根据施加在可编程逻辑电路上的处理能力自动改变时钟频率和工作电压，降低功耗的逻辑电路系统。 可编程逻辑电路能够动态地实现多个电路功能，并且可以在操作期间改变实现的电路功能。 此外，系统具有用于向可编程逻辑电路提供电压的电压供应部分，用于向可编程逻辑电路提供时钟信号的时钟信号提供部分，用于改变可编程逻辑实现的电路功能的改变控制部分 电路中的任何一个电路功能，操作时间测量部分，用于分别测量可编程逻辑电路的操作时间以执行分别执行电路功能的处理;以及时钟和电压确定部分，用于确定 时钟信号和电压，使用操作时间。

公开(公告)号：US20050110518A1

公开(公告)日：2005-05-26

申请号：US10948702

申请日：2004-09-24

申请人： Shinichi Kanno ,  Yukimasa Miyamoto ,  Masaya Tarui ,  Taku Ooneda

发明人： Shinichi Kanno ,  Yukimasa Miyamoto ,  Masaya Tarui ,  Taku Ooneda

IPC分类号： G06F11/00 ,  G06F9/06 ,  G06F15/76 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F17/5054

摘要： A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.

摘要翻译： 一种分时处理能力的逻辑电路装置，包括一个电路布置信息存储器，该电路布置信息存储器存储与多个单元电路中的每一个相对应的电路布置信息，以及一个可编程逻辑电路，该电路布置可以是 通过在可编程逻辑电路正在运行时采用电路布置信息来重新配置，存储输入数据和与每个电路的处理操作相关的输出数据的处理数据存储器，以及监视输入的存储量的控制器 数据和/或对应于每个单元电路的输出数据的存储量，并且当存储量满足一定条件时，控制可编程逻辑电路的电路装置的重新配置。

公开(公告)号：US07474119B2

公开(公告)日：2009-01-06

申请号：US10948702

申请日：2004-09-24

申请人： Shinichi Kanno ,  Yukimasa Miyamoto ,  Masaya Tarui ,  Taku Ooneda

发明人： Shinichi Kanno ,  Yukimasa Miyamoto ,  Masaya Tarui ,  Taku Ooneda

IPC分类号： G06F7/38 ,  H03F19/173

CPC分类号： G06F17/5054

摘要： A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.

摘要翻译： 一种分时处理能力的逻辑电路装置，包括一个电路布置信息存储器，该电路布置信息存储器存储与多个单元电路中的每一个相对应的电路布置信息，以及一个可编程逻辑电路，该电路布置可以是 通过在可编程逻辑电路正在运行时采用电路布置信息来重新配置，存储输入数据和与每个电路的处理操作相关的输出数据的处理数据存储器，以及监视输入的存储量的控制器 数据和/或对应于每个单元电路的输出数据的存储量，并且当存储量满足一定条件时，控制可编程逻辑电路的电路装置的重新配置。

公开(公告)号：US20080016376A1

公开(公告)日：2008-01-17

申请号：US11778404

申请日：2007-07-16

申请人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto

发明人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto

IPC分类号： G06F1/26

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3296 ,  H03K19/0008 ,  H03K19/0016 ,  H03K19/1736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17784 ,  H03K19/17788 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.

摘要翻译： 通过根据施加在可编程逻辑电路上的处理能力自动改变时钟频率和工作电压，降低功耗的逻辑电路系统。 可编程逻辑电路能够动态地实现多个电路功能，并且可以在操作期间改变实现的电路功能。 此外，系统具有用于向可编程逻辑电路提供电压的电压供应部分，用于向可编程逻辑电路提供时钟信号的时钟信号提供部分，用于改变可编程逻辑实现的电路功能的改变控制部分 电路中的任何一个电路功能，操作时间测量部分，用于分别测量可编程逻辑电路的运行时间以分别执行处理以实现电路功能;以及时钟和电压确定部分，用于确定 时钟信号和电压，使用操作时间。