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    Method for generating logic circuit data
    5.
    发明授权
    Method for generating logic circuit data 失效
    用于产生逻辑电路数据的方法

    公开(公告)号：US4758953A

    公开(公告)日：1988-07-19

    申请号：US102771

    申请日：1987-09-23

    申请人： Masato Morita ,  Yukio Ikariya ,  Yoshinori Sakataya ,  Masayuki Miyoshi

    发明人： Masato Morita ,  Yukio Ikariya ,  Yoshinori Sakataya ,  Masayuki Miyoshi

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G06T5/00 ,  G06F15/60

    CPC分类号： G06F17/5022

    摘要： In automatic development of the higher hierarchic logic into the lower hierarchic logic in a hierarchic logic designing, identification codes are beforehand assigned to logic components of the higher hierarchic logic, and the identification codes are also assigned to the lower hierarchic logic data when developing the higher hierarchic logic into the lower hierarchic logic in order to establish correspondences between the higher and lower hierarchic logic, thereby allowing a higher-speed logic compare operation with respect to a design change on the higher or lower hierarchic logic and enabling the automatic update of the lower hierarchic logic by use of the higher hierarchic logic as the master.

    摘要翻译： 在分级逻辑设计中将较高层次逻辑自动开发成较低等级的逻辑时，将识别码预先分配给较高层次逻辑的逻辑组件，并且当开发较高级逻辑数据时，识别码也被分配给较低分级逻辑数据 分层逻辑转换为较低级别的逻辑，以便建立较高和较低级别逻辑之间的对应关系，从而允许相对于较高或较低级别逻辑上的设计更改进行更高速度的逻辑比较操作，并使得能够自动更新较低级 通过使用较高级别的逻辑作为主人的分级逻辑。

    Method of digital logic simulation
    9.
    发明授权
    Method of digital logic simulation 失效
    数字逻辑仿真方法

    公开(公告)号：US4342093A

    公开(公告)日：1982-07-27

    申请号：US149547

    申请日：1980-05-13

    申请人： Masayuki Miyoshi

    发明人： Masayuki Miyoshi

    IPC分类号： G06F11/25 ,  G06F9/34 ,  G06F17/50 ,  G06F15/20

    CPC分类号： G06F17/5022

    摘要： A logic simulation is executed using a real circuit as a part of a simulation model of a logic circuit subjected to the logic simulation. The simulation model is formed of the real circuit and a simulation circuit, and the operation of the real circuit and the logic simulation of the simulation circuit are performed alternately. The operation of the real circuit is performed in response to an input signal thereto representing the condition of the output node of the simulation circuit, while the logic simulation of the simulation circuit is executed in response to a stimulus in the form of an output signal of the real circuit which is applied to the input node of the simulation circuit.

    摘要翻译： 使用实际电路作为经过逻辑仿真的逻辑电路的仿真模型的一部分来执行逻辑仿真。 仿真模型由实际电路和仿真电路组成，仿真电路的运行和仿真电路的逻辑仿真交替进行。 响应于表示模拟电路的输出节点的状态的输入信号，执行实际电路的操作，同时响应于输出信号形式的刺激来执行模拟电路的逻辑模拟， 应用于仿真电路的输入节点的实际电路。