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    Data-driven processor having an internal tag-generating system for generating a distinct tagged information and assembling with un-tagged information of an input/output data packet
    1.
    发明授权
    Data-driven processor having an internal tag-generating system for generating a distinct tagged information and assembling with un-tagged information of an input/output data packet 失效
    数据驱动处理器具有内部标签生成系统，用于生成不同的标记信息并且与输入/输出数据包的未标记信息进行组合

    公开(公告)号：US5117489A

    公开(公告)日：1992-05-26

    申请号：US471684

    申请日：1990-01-26

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4436

    摘要： A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved and the data output is executed in a predetermined order.

    摘要翻译： 数据驱动处理器具有分组组合单元，用于当输入数据不具有诸如目的地址等的标签信息时，将标签信息添加到顺序输入的数据，从而使得能够在不使用外部电路的情况下输入数据 ，诸如主处理器，并且提高数据输入速率，并且还具有分组输出和重排单元，用于以预定顺序重新排列输出分组流，从而仅输出数据信息，使得数据可能是 在没有任何外部电路的情况下输出，例如主机处理器，输出速率得到改善，并且以预定顺序执行数据输出。

    Data-driven processor having an output unit for providing only operand data in a predetermined order
    2.
    发明授权
    Data-driven processor having an output unit for providing only operand data in a predetermined order 失效
    数据驱动处理器具有用于仅以预定顺序提供操作数数据的输出单元

    公开(公告)号：US5392442A

    公开(公告)日：1995-02-21

    申请号：US837128

    申请日：1992-02-19

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    IPC分类号： E04B1/41 ,  F16B13/08 ,  F16B13/14 ,  G06F9/06

    CPC分类号： F16B13/0808 ,  Y10S411/908

    摘要： A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved, and the data output is executed in a predetermined order.

    摘要翻译： 数据驱动处理器具有分组组合单元，用于当输入数据不具有诸如目的地址等的标签信息时，将标签信息添加到顺序输入的数据，从而使得能够在不使用外部电路的情况下输入数据 ，诸如主处理器，并且提高数据输入速率，并且还具有分组输出和重排单元，用于以预定顺序重新排列输出分组流，从而仅输出数据信息，使得数据可能是 在没有任何外部电路的情况下输出，诸如主处理器，输出速率得到改善，并且以预定顺序执行数据输出。

    Bus connection detector circuit for bus connection matrix circuit
    8.
    发明授权
    Bus connection detector circuit for bus connection matrix circuit 失效
    总线连接检测电路总线连接矩阵电路

    公开(公告)号：US4151374A

    公开(公告)日：1979-04-24

    申请号：US794706

    申请日：1977-05-09

    申请人： Takeshi Fukuhara ,  Yuji Miura

    发明人： Takeshi Fukuhara ,  Yuji Miura

    IPC分类号： G01R19/145 ,  H03K17/00 ,  H04Q3/52

    CPC分类号： H04Q3/521

    摘要： A bus connection detector circuit used for a switching network comprising a plurality of semiconductor switch elements of PNPN semiconductor four-layered structure, which are arranged in a matrix array and adapted to conduct upon the application of a potential thereacross. A plurality of diodes are connected at their one end to horizontal and vertical buses, respectively, and connected at their other end in common to one end of a voltage regulating diode for detection of the potential of the buses, and the other end of the voltage regulating diode is connected to a voltage level sensor, thus making up a single bus connection detector circuit, so that the connection of each bus can be detected by the single bus connection detector circuit.

    摘要翻译： 一种用于交换网络的总线连接检测器电路，包括PNPN半导体四层结构的多个半导体开关元件，它们以矩阵阵列排列并且适于在施加其上的电位时进行导通。 多个二极管的一端分别连接到水平和垂直总线，并在其另一端共同连接到电压调节二极管的一端，用于检测总线的电位，另一端的电压 调节二极管连接到电压电平传感器，从而构成单总线连接检测器电路，使得每个总线的连接可以由单总线连接检测器电路检测。

    Current supply system for terminal devices
    10.
    发明授权
    Current supply system for terminal devices 失效
    终端设备供电系统

    公开(公告)号：US4035586A

    公开(公告)日：1977-07-12

    申请号：US660780

    申请日：1976-02-24

    申请人： Hirotoshi Shirasu ,  Hidetaka Yamashita ,  Tatsumasa Oonuma ,  Takeshi Fukuhara

    发明人： Hirotoshi Shirasu ,  Hidetaka Yamashita ,  Tatsumasa Oonuma ,  Takeshi Fukuhara

    IPC分类号： H04M19/00 ,  H04Q1/28

    CPC分类号： H04M19/00 ,  H04M19/001

    摘要： A current supply system for terminal devices in which the line circuits are divided into groups in accordance with the line impedance thereof between an exchange or switching network and respective terminal devices or telephone sets, and a different voltage is applied to respective groups of line circuits which corresponds to the current matching the line impedance for the respective groups of line circuits.

    摘要翻译： 一种用于终端设备的电流供应系统，其中根据交换机或交换网络与相应的终端设备或电话机之间的线路阻抗将线路电路分成几组，并且将不同的电压施加到相应的线路电路组 对应于相应的线路电路组的线路阻抗匹配的电流。