公开(公告)号：US5072377A

公开(公告)日：1991-12-10

申请号：US121516

申请日：1987-11-17

Applicant: Fumiyasu Asai ,  Shinji Komori

Inventor： Fumiyasu Asai ,  Shinji Komori

IPC: G06F15/82 ,  G06F9/44 ,  G06F12/00

CPC classification number: G06F9/4436

Abstract: A data driven processing system includes a mechanism for generating a data pair from a sequential input data stream by matching identifier fields. The pairing mechanism comprises a hash memory in which input data words to be paired are stored by using hashed addresses. If a hash collision occurs, the data word which caused the hash collision is transmitted to a counter-directional data loop which is used to generate a data pair. If an input data word is not paired after one pass through the data loop it is returned to the hash memory for another pairing operation. Use of both the hash memory and the counter-directional data loop reduces the required hash memory size and increases processing efficiency.

Abstract translation: 数据驱动处理系统包括用于通过匹配标识符字段从顺序输入数据流生成数据对的机制。 配对机制包括散列存储器，其中通过使用散列地址来存储要配对的输入数据字。 如果发生哈希冲突，则导致哈希冲突的数据字被发送到用于生成数据对的逆向数据循环。 如果输入数据字在一次通过数据循环后未配对，则返回到哈希存储器进行另一次配对操作。 使用散列存储器和逆向数据环路都可以减少所需的散列存储器大小并提高处理效率。

公开(公告)号：US4841436A

公开(公告)日：1989-06-20

申请号：US868701

申请日：1986-05-30

Applicant: Hajime Asano ,  Hiroaki Terada ,  Katsuhiko Asada ,  Hiroaki Nishikawa ,  Masahisa Shimizu ,  Hiroki Miura ,  Kenji Shima ,  Shinji Komori ,  Souichi Miyata ,  Satoshi Matsumoto

Inventor： Hajime Asano ,  Hiroaki Terada ,  Katsuhiko Asada ,  Hiroaki Nishikawa ,  Masahisa Shimizu ,  Hiroki Miura ,  Kenji Shima ,  Shinji Komori ,  Souichi Miyata ,  Satoshi Matsumoto

IPC: G06F15/82 ,  G06F9/44

CPC classification number: G06F9/4436

Abstract: A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.

Abstract translation: 描述了使用标记令牌方案的数据流计算机中使用的标签数据处理装置。 通过使用流水线寄存器，队列存储器和简单控制电路来执行标签添加处理和标签恢复处理，从而获得高速操作和优异的吞吐量，而不需要标签存储表，复杂的操作测试电路或序列控制电路 。

公开(公告)号：US4785204A

公开(公告)日：1988-11-15

申请号：US875551

申请日：1986-06-18

Applicant: Hiroaki Terada ,  Katsuhiko Asada ,  Niroaki Nishikawa ,  Shinji Komori ,  Kenji Shima ,  Souichi Miyata ,  Satoshi Matsumoto ,  Hajime Asano ,  Masahisa Shimizu ,  Hiroki Miura

Inventor： Hiroaki Terada ,  Katsuhiko Asada ,  Niroaki Nishikawa ,  Shinji Komori ,  Kenji Shima ,  Souichi Miyata ,  Satoshi Matsumoto ,  Hajime Asano ,  Masahisa Shimizu ,  Hiroki Miura

IPC: H03K19/21 ,  H03K3/353 ,  H03K3/286 ,  H03K21/17 ,  H03K23/44

CPC classification number: H03K19/215

Abstract: A coincidence element responsive to a plurality of input signals for outputting the level of the input signals when said plurality of input signals coincide with each other includes, a serial connection of a first electrically conductive type and a second electrically conductive type MOS transistors of the same number, the number being equal to the number of the input signals, responsive to said plurality of inputs connected between a first power supply and a second power supply; and a CMOS inverter responsive to an intermediate output at the connection of the most lower stage first conductivity type MOS transistor and the most upper stage second conductivity type MOS transistor for outputting a coincidence signal.

Abstract translation: 当所述多个输入信号彼此一致时，响应于多个输入信号用于输出输入信号的电平的符合元件包括：第一导电类型和第二导电类型的MOS晶体管的串联连接 数量等于输入信号的数量，响应于连接在第一电源和第二电源之间的所述多个输入; 以及响应于在最下级第一导电类型MOS晶体管和最上层第二导电类型MOS晶体管的连接处的中间输出的CMOS反相器，用于输出一致信号。

公开(公告)号：US4080289A

公开(公告)日：1978-03-21

申请号：US657560

申请日：1976-02-12

Applicant: Katsuya Ebara ,  Toshio Ogawa ,  Sankichi Takahashi ,  Sigeoki Nishimura ,  Seiichi Kikkawa ,  Shinji Komori ,  Toshio Sawa

Inventor： Katsuya Ebara ,  Toshio Ogawa ,  Sankichi Takahashi ,  Sigeoki Nishimura ,  Seiichi Kikkawa ,  Shinji Komori ,  Toshio Sawa

IPC: B01D65/04 ,  C02F1/44 ,  C02F1/68 ,  C02F5/08 ,  B01D13/00 ,  B01D5/00 ,  B01D11/00

CPC classification number: C02F5/083 ,  B01D61/08 ,  B01D63/06 ,  B01D65/08 ,  C02F1/683 ,  B01D2321/168

Abstract: A system is provided for separating waste water or solution into a permea solution and a concentrated solution by feeding the waste water or solution to a reverse osmosis apparatus using a membrane.A chemical pretreating apparatus is provided to prevent hard scales contained in the waste water or solution from precipitation during the concentration in the reverse osmosis apparatus using the membrane. An apparatus for charging sponge balls is further provided to mechanically remove suspended solids and other suspended matters, that is, soft scales when deposited on the surface of membrane. The sponge balls are desirably recyclically used.

Abstract translation: 提供了一种用于通过使用膜将废水或溶液供给到反渗透装置来将废水或溶液分离成渗透溶液和浓缩溶液的系统。

公开(公告)号：US5740463A

公开(公告)日：1998-04-14

申请号：US504583

申请日：1995-07-20

Applicant: Takeharu Oshima ,  Toshiyuki Tamura ,  Satoru Kotoh ,  Hirono Tsubota ,  Shinji Komori ,  Shinji Nakashima ,  Hiroaki Terada ,  Makoto Iwata ,  Katsuhito Yamaguchi ,  Junji Onishi ,  Akira Kondo

Inventor： Takeharu Oshima ,  Toshiyuki Tamura ,  Satoru Kotoh ,  Hirono Tsubota ,  Shinji Komori ,  Shinji Nakashima ,  Hiroaki Terada ,  Makoto Iwata ,  Katsuhito Yamaguchi ,  Junji Onishi ,  Akira Kondo

IPC: G06F15/173 ,  G06F15/80 ,  G06F15/82 ,  G06F17/13 ,  G06F13/38 ,  G06F15/16

CPC classification number: G06F15/803 ,  G06F17/13

Abstract: Intercommunication of data between adjacent element processors (3) is performed through a memory unit (6) which is independently accessible to the respective element processors (3) without interfere with the operations of the other element processors (3). Thus, memory access and data transfer can be achieved without interfere with the operations of individual element processor (3). Furthermore, it becomes possible to solve differential equations by asynchronous communication system.

Abstract translation: 相邻元件处理器（3）之间的数据互通是通过对各个元件处理器（3）可独立访问的存储器单元执行的，而不干扰其它元件处理器（3）的操作。 因此，可以在不干扰单个元件处理器（3）的操作的情况下实现存储器访问和数据传送。 此外，可以通过异步通信系统求解微分方程。

公开(公告)号：US5341507A

公开(公告)日：1994-08-23

申请号：US729727

申请日：1991-07-15

Applicant: Hiroaki Terada ,  Hiroaki Nishikawa ,  Tetsuo Yamasaki ,  Yoshie Inaoka ,  Kenji Shima ,  Shinji Komori ,  Shin-ichi Yoshida ,  Shunji Hine ,  Youichiro Nishikawa ,  Shuji Hara

Inventor： Hiroaki Terada ,  Hiroaki Nishikawa ,  Tetsuo Yamasaki ,  Yoshie Inaoka ,  Kenji Shima ,  Shinji Komori ,  Shin-ichi Yoshida ,  Shunji Hine ,  Youichiro Nishikawa ,  Shuji Hara

IPC: G06F15/16 ,  G06F9/44 ,  G06F15/82

CPC classification number: G06F9/4436 ,  G06F15/82

Abstract: In a data driven type information processing apparatus, an operation processing unit. The operation processing unit executes processing of a high function instruction on the basis of corresponding information stored in a specification data memory, and branches data packets, received from a pair data detecting unit, to a simple instruction processing unit. The apparatus further includes a junction unit for joining data packets outputted from the high function and the simple function instruction processing units to output them to an output unit.

Abstract translation: 在数据驱动型信息处理装置中，操作处理单元。 操作处理单元基于存储在指定数据存储器中的对应信息执行高功能指令的处理，并将从对数据检测单元接收的数据分组分支到简单指令处理单元。 该装置还包括用于连接从高功能输出的数据分组和简单功能指令处理单元的接合单元，以将它们输出到输出单元。

公开(公告)号：US5321387A

公开(公告)日：1994-06-14

申请号：US99803

申请日：1993-07-29

Applicant: Hiroaki Terada ,  Katsuhiko Asada ,  Hiroaki Nishikawa ,  Souichi Miyata ,  Satoshi Matsumoto ,  Hajime Asano ,  Masahisa Shimizu ,  Hiroki Miura ,  Kenji Shima ,  Shinji Komori

Inventor： Hiroaki Terada ,  Katsuhiko Asada ,  Hiroaki Nishikawa ,  Souichi Miyata ,  Satoshi Matsumoto ,  Hajime Asano ,  Masahisa Shimizu ,  Hiroki Miura ,  Kenji Shima ,  Shinji Komori

IPC: G06F15/173 ,  G11C15/00 ,  G11C19/00 ,  G06F7/04 ,  G06F7/06

CPC classification number: G06F15/17337 ,  G11C15/00 ,  G11C19/00

Abstract: An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets each having identification data are transmitted to respective stages of the shift register. The identification data are extracted from the data packets transmitted on the shift registers and compared with each other in a comparing circuit. If and when the identification data of two data packets respectively transmitted on the respective transmission paths are coincident, those two data packets are determined as the data packets to be paired. The data packet pair is read from the data transmission paths.

Abstract translation: 关联存储器包括两个数据传输路径，每个数据传输路径包括以循环方式形成的自运行移位寄存器。 在相应的数据传输路径中，每个具有识别数据的数据包被发送到移位寄存器的各个级。 从移位寄存器上发送的数据包中提取识别数据，并在比较电路中进行比较。 如果并且当在各个传输路径上分别发送的两个数据分组的识别数据一致时，那两个数据分组被确定为要配对的数据分组。 从数据传输路径读取数据包对。

公开(公告)号：US5182799A

公开(公告)日：1993-01-26

申请号：US416887

申请日：1989-10-04

Applicant: Toshiyuki Tamura ,  Masaki Fujita ,  Shinji Komori ,  Hisakazu Sato ,  Hidehiro Takata

Inventor： Toshiyuki Tamura ,  Masaki Fujita ,  Shinji Komori ,  Hisakazu Sato ,  Hidehiro Takata

IPC: G06F15/82 ,  G06F9/44 ,  G06F17/30

CPC classification number: G06F17/30949 ,  G06F9/4436

Abstract: A data retrieving apparatus having an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in response to the result of judgement of said associative memory unit.

Abstract translation: 一种数据检索装置，具有地址发生器，用于当输入具有操作数据和多个识别数据的分组时，部分地选择识别数据的比特串中的一个以及通过其可逆操作产生散列的地址，哈希存储器 用于通过散列地址访问的匹配检测器，用于将存储的分组的识别数据与输入的分组的识别数据进行比较，并且当有效分组已经存储在从输入分组生成的散列地址中时，判断匹配/不匹配 相关联存储单元，用于当匹配检测器判断为不匹配时，将输入的分组的识别数据存储为检索数据，并且当分组是分组时，判断已经存储的识别数据与输入分组的识别数据的匹配/不匹配 以及用于选择来自散列存储器或关联存储器uni的输出的输出选择器 响应于所述关联存储器单元的判断结果。

公开(公告)号：US4953083A

公开(公告)日：1990-08-28

申请号：US373616

申请日：1989-06-28

Applicant: Hidehiro Takata ,  Shinji Komori ,  Toshiyuki Tamura ,  Tetsuo Yamasaki ,  Kenji Shima

Inventor： Hidehiro Takata ,  Shinji Komori ,  Toshiyuki Tamura ,  Tetsuo Yamasaki ,  Kenji Shima

IPC: G06F9/44

CPC classification number: G06F9/4436

Abstract: An improved data driven processor that utilizes queue buffers in the data path to maintain optimal dataflow.

Abstract translation: 改进的数据驱动处理器利用数据路径中的队列缓冲器来保持最佳数据流。

公开(公告)号：US4943916A

公开(公告)日：1990-07-24

申请号：US361701

申请日：1989-06-01

Applicant: Hajime Asano ,  Hiroaki Terada ,  Katsuhiko Asada ,  Hiroaki Nishikawa ,  Masahisa Shimizu ,  Hiroki Miura ,  Kenji Shima ,  Shinji Komori ,  Souichi Miyata ,  Satoshi Matsumoto

Inventor： Hajime Asano ,  Hiroaki Terada ,  Katsuhiko Asada ,  Hiroaki Nishikawa ,  Masahisa Shimizu ,  Hiroki Miura ,  Kenji Shima ,  Shinji Komori ,  Souichi Miyata ,  Satoshi Matsumoto

IPC: G06F15/82 ,  G06F9/38 ,  G06F9/44

CPC classification number: G06F9/4436 ,  G06F9/38

Abstract: By providing a tag data renewing unit in a data flow-computer, the "delay" function, which is necessary for a digital filter, etc., can be realized, and it is unnecessary to keep the order relation for tokens with respect to first-in/first-out, which must be kept at respective points in a conventional data flow computer, and thereby the architecture of a compiler can be simplified and at the same time the execution time can be shortened.

Abstract translation: 通过在数据流计算机中提供标签数据更新单元，可以实现数字滤波器等所必需的“延迟”功能，并且不需要保持令牌相对于第一 -in / first-out，其必须保存在常规数据流计算机的各个点处，从而可以简化编译器的架构，同时可以缩短执行时间。