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公开(公告)号：US09251055B2
公开(公告)日：2016-02-02
申请号：US13599087
申请日：2012-08-30
申请人： Shinji Yonezawa , Takashi Hirao , Hirokuni Yano , Mitsunori Tadokoro , Hiroki Matsudaira , Akira Sawaoka
发明人： Shinji Yonezawa , Takashi Hirao , Hirokuni Yano , Mitsunori Tadokoro , Hiroki Matsudaira , Akira Sawaoka
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205 , G06F2212/7209 , G11C2211/5641
摘要： A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.
摘要翻译： 实施例中的存储器系统包括存储用户数据的非易失性半导体存储器，正向查找地址转换表和反向查找地址转换表以及控制器。 控制器被配置为基于这两个表来确定存储在非易失性半导体存储器中的用户数据有效或无效。 控制器可以执行数据组织，选择确定有效的数据并在新的块中重写数据。 控制器可以以预定的比例交替地对新的块执行写入处理和重写处理。 当条件满足时，控制器可以基于写入请求中包括的地址和写入数据来确定是否满足预定条件，并且当条件不满足时将控制器写入SLC模式中的数据。
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2.发明授权Management information generating method, logical block constructing method, and semiconductor memory device 有权管理信息生成方法，逻辑块构造方法和半导体存储器件公开(公告)号：US08924636B2
公开(公告)日：2014-12-30
申请号：US13609991
申请日：2012-09-11
申请人： Takashi Hirao , Hirokuni Yano , Aurelien Nam Phong Tran , Mitsunori Tadokoro , Hiroki Matsudaira , Tatsuya Sumiyoshi , Yoshimi Niisato , Kenji Tanaka
发明人： Takashi Hirao , Hirokuni Yano , Aurelien Nam Phong Tran , Mitsunori Tadokoro , Hiroki Matsudaira , Tatsuya Sumiyoshi , Yoshimi Niisato , Kenji Tanaka
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/1032 , G06F2212/7201 , G11C16/349
摘要： A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, a value is set for a maximum number of allowable defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.
摘要翻译： 一种管理信息生成方法，其中连续地址的逻辑和物理块地址（BA）在BA转换表中彼此相关联。 当构建逻辑块时，为允许的有缺陷的物理块的最大数量设置一个值。 具有比设定号码少的缺陷的逻辑块被设置为可用，并且具有比设定号码多的缺陷的逻辑块被设置为不可用。 执行系统逻辑块构造以从包括大量可用块的平面列表中优先选择物理块以均衡每个平面列表中的可用块的数量。 基于第一管理单元确定空闲块的数量是否不足，以及是否可以基于与第一单元不同的管理单元来保留指示容量的存储区域。
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公开(公告)号：US20110231734A1
公开(公告)日：2011-09-22
申请号：US13152962
申请日：2011-06-03
IPC分类号： G06F11/16
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0679 , G06F11/1072 , G11C16/06 , G11C29/52 , G11C29/78 , G11C2029/0411
摘要： A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.
摘要翻译： 存储器系统包括控制单元，其被配置为控制第一和第二存储器之间的数据传输。 控制单元执行复制处理，在将第二存储器的第一页中存储的数据读出到第一存储器之后，将数据写入第二存储器的第二页，在执行复制处理时确定纠错 从第一页读出的数据的处理成功，当纠错处理成功时存储第一存储器中的校正数据并将修正数据写入第二页，并且当纠错处理失败时读出 ，从第一页到第一存储器的数据，并将未经过纠错处理的数据写入第二页。
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公开(公告)号：US20210166239A1
公开(公告)日：2021-06-03
申请号：US17156854
申请日：2021-01-25
申请人： Hiroki Matsudaira
发明人： Hiroki Matsudaira
IPC分类号： G06Q20/40 , G06Q20/06 , G06Q30/06 , G06F16/955
摘要： Provided is an environment in which balance information can be easily confirmed when a virtual currency is settled. The intermediary web page 110 corresponds to a URL address based on the merchandise identification information of the merchandise selected by a purchaser on the merchant web page 100. The authentication unit 120 authenticates the purchaser who has accessed the intermediary web page via the merchant web page 100. The acquisition unit 130 accesses the block chain based on the registration information of the purchaser authenticated by the authentication unit 120 to acquire the balance information of the virtual currency of the purchaser. The reflecting unit 140 reflects the balance information acquired by the acquiring unit 130 on the intermediary web page 110.
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公开(公告)号：US08108594B2
公开(公告)日：2012-01-31
申请号：US12529223
申请日：2009-02-10
IPC分类号： G06F12/00
CPC分类号： G06F11/1435 , G06F11/1441 , G06F11/1471 , G06F11/1474
摘要： To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (1)” for a pre-log, when a program error occurs when data writing is being performed (a data writing error), the memory system performs the data writing again without acquiring a pre-log corresponding to data rewriting processing. After finishing the data writing, the memory system acquires, without generating a post-log, a snapshot instead of the post-log and finishes the processing.
摘要翻译： 提供即使在数据写入过程中发生程序错误时也可以确保还原管理信息的存储系统。 在“日志写入（1）”作为预登录之后，当执行数据写入时发生程序错误（数据写入错误）时，存储器系统再次执行数据写入，而不获取对应于数据重写的预记录 处理。 在完成数据写入之后，内存系统在不生成后记录的情况下获取快照而不是后记录，并完成处理。
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公开(公告)号：US20090241010A1
公开(公告)日：2009-09-24
申请号：US12394665
申请日：2009-02-27
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0679 , G06F11/1072 , G11C16/06 , G11C29/52 , G11C29/78 , G11C2029/0411
摘要： A memory system includes a controller that manages data stored in the first and second storing areas. The controller determines, when a readout error occurs when the stored data in the second storing area is read out, success or failure of error correction to the read-out data based on the result of the error correction stored in a storage buffer, writes, when the error correction is successful, correction data corresponding to the read-out data stored in the storage buffer, and writes, when the error correction fails, the read-out data itself not subjected to error correction processing.
摘要翻译： 存储器系统包括管理存储在第一和第二存储区域中的数据的控制器。 当存储在第二存储区域中的数据被读出时，控制器基于存储在存储缓冲器中的纠错结果对读出的数据进行错误校正的成功或失败， 当纠错成功时，对应于存储在存储缓冲器中的读出数据的校正数据，并且当纠错失败时，读出数据本身不进行纠错处理。
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公开(公告)号：US20130246689A1
公开(公告)日：2013-09-19
申请号：US13609663
申请日：2012-09-11
申请人： Hiroki Matsudaira , Ryuji Nishikubo
发明人： Hiroki Matsudaira , Ryuji Nishikubo
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/401 , G06F2212/7201 , G06F2212/7207
摘要： According to one embodiment, a memory system includes a non-volatile memory, a volatile memory, a controller, and a compression/decompression processor. When data transmission is performed through the volatile memory between a host apparatus and the non-volatile memory, the controller updates management information stored in the volatile memory. In addition, the compression/decompression processor compresses the management information in the case where a first condition is satisfied, and decompresses the compressed management information in the case where a second condition is satisfied. The controller stores the compressed management information in the non-volatile memory.
摘要翻译： 根据一个实施例，存储器系统包括非易失性存储器，易失性存储器，控制器和压缩/解压缩处理器。 当通过主机设备和非易失性存储器之间的易失性存储器执行数据传输时，控制器更新存储在易失性存储器中的管理信息。 此外，在满足第一条件的情况下，压缩/解压缩处理器压缩管理信息，并且在满足第二条件的情况下解压缩压缩管理信息。 控制器将压缩的管理信息存储在非易失性存储器中。
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公开(公告)号：US20100153626A1
公开(公告)日：2010-06-17
申请号：US12529223
申请日：2009-02-10
CPC分类号： G06F11/1435 , G06F11/1441 , G06F11/1471 , G06F11/1474
摘要： To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (1)” for a pre-log, when a program error occurs when data writing is being performed (a data writing error), the memory system performs the data writing again without acquiring a pre-log corresponding to data rewriting processing. After finishing the data writing, the memory system acquires, without generating a post-log, a snapshot instead of the post-log and finishes the processing.
摘要翻译： 提供即使在数据写入过程中发生程序错误时也可以确保还原管理信息的存储系统。 在“日志写入（1）”作为预登录之后，当执行数据写入时发生程序错误（数据写入错误）时，存储器系统再次执行数据写入，而不获取对应于数据重写的预记录 处理。 在完成数据写入之后，内存系统在不生成后记录的情况下获取快照而不是后记录，并完成处理。
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公开(公告)号：US09047177B2
公开(公告)日：2015-06-02
申请号：US13609663
申请日：2012-09-11
申请人： Hiroki Matsudaira , Ryuji Nishikubo
发明人： Hiroki Matsudaira , Ryuji Nishikubo
CPC分类号： G06F12/0246 , G06F2212/401 , G06F2212/7201 , G06F2212/7207
摘要： According to one embodiment, a memory system includes a non-volatile memory, a volatile memory, a controller, and a compression/decompression processor. When data transmission is performed through the volatile memory between a host apparatus and the non-volatile memory, the controller updates management information stored in the volatile memory. In addition, the compression/decompression processor compresses the management information in the case where a first condition is satisfied, and decompresses the compressed management information in the case where a second condition is satisfied. The controller stores the compressed management information in the non-volatile memory.
摘要翻译： 根据一个实施例，存储器系统包括非易失性存储器，易失性存储器，控制器和压缩/解压缩处理器。 当通过主机设备和非易失性存储器之间的易失性存储器执行数据传输时，控制器更新存储在易失性存储器中的管理信息。 此外，在满足第一条件的情况下，压缩/解压缩处理器压缩管理信息，并且在满足第二条件的情况下解压缩压缩管理信息。 控制器将压缩的管理信息存储在非易失性存储器中。
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10.发明授权Nonvolatile semiconductor memory system configured to control data transfer 失效配置为控制数据传输的非易失性半导体存储器系统公开(公告)号：US08751901B2
公开(公告)日：2014-06-10
申请号：US13152962
申请日：2011-06-03
IPC分类号： G11C29/42
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0679 , G06F11/1072 , G11C16/06 , G11C29/52 , G11C29/78 , G11C2029/0411
摘要： A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.
摘要翻译： 存储器系统包括控制单元，其被配置为控制第一和第二存储器之间的数据传输。 控制单元执行复制处理，在将第二存储器的第一页中存储的数据读出到第一存储器之后，将数据写入第二存储器的第二页，在执行复制处理时确定纠错 从第一页读出的数据的处理成功，当纠错处理成功时存储第一存储器中的校正数据并将修正数据写入第二页，并且当纠错处理失败时读出 ，从第一页到第一存储器的数据，并将未经过纠错处理的数据写入第二页。
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