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公开(公告)号：US07805553B2
公开(公告)日：2010-09-28
申请号：US11604011
申请日：2006-11-22
CPC分类号： G06F13/385
摘要： An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.
摘要翻译： 集成电路装置包括包括主机操作所必需的电路和设备操作所需的电路的公共收发器宏单元。 公共收发器宏单元包括模拟前端电路和高速逻辑电路。 高速逻辑电路包括并行/串行转换电路，用作外部电路和并行/串行转换电路之间的接口的第一并行接口，采样时钟产生电路，串行/并行转换电路和 第二并行接口，其用作串行/并行转换电路和外部电路之间的接口。
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公开(公告)号：US20070156932A1
公开(公告)日：2007-07-05
申请号：US11604011
申请日：2006-11-22
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.
摘要翻译： 集成电路装置包括包括主机操作所必需的电路和设备操作所需的电路的公共收发器宏单元。 公共收发器宏单元包括模拟前端电路和高速逻辑电路。 高速逻辑电路包括并行/串行转换电路，用作外部电路和并行/串行转换电路之间的接口的第一并行接口，采样时钟产生电路，串行/并行转换电路和 第二并行接口，用作串行/并行转换电路和外部电路之间的接口。
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公开(公告)号：US07477615B2
公开(公告)日：2009-01-13
申请号：US11244046
申请日：2005-10-06
CPC分类号： H04L25/0272
摘要： A transceiver includes upstream differential signal lines DPUP and DMUP, downstream differential signal lines DPDW and DMDW, common differential signal lines DPCM and DMCM, a first transmission driver of which outputs are connected to DPUP and DMUP, a second transmission driver of which outputs are connected to DPDW and DMDW, a first switch circuit which connects the first transmission driver to a logic circuit during upstream connection and connects the second transmission driver to the logic circuit during downstream connection, a second switch circuit which respectively connects DPUP and DMUP to DPCM and DMCM during the upstream connection and respectively connects DPDW and DMDW to DPCM and DMCM during the downstream connection, and a third transmission driver connected to DPCM and DMCM.
摘要翻译： 收发器包括上游差分信号线DPUP和DMUP，下游差分信号线DPDW和DMDW，公共差分信号线DPCM和DMCM，其输出连接到DPUP和DMUP的第一传输驱动器，连接有输出的第二传输驱动器 DPDW和DMDW，第一开关电路，其在上游连接期间将第一传输驱动器连接到逻辑电路，并且在下游连接期间将第二传输驱动器连接到逻辑电路;第二开关电路，分别将DPUP和DMUP连接到DPCM和DMCM 在上游连接期间，并且在下游连接期间分别将DPDW和DMDW连接到DPCM和DMCM，以及连接到DPCM和DMCM的第三传输驱动器。
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公开(公告)号：US20060077916A1
公开(公告)日：2006-04-13
申请号：US11244046
申请日：2005-10-06
IPC分类号： H04L5/22
CPC分类号： H04L25/0272
摘要： A transceiver includes upstream differential signal lines DPUP and DMUP, downstream differential signal lines DPDW and DMDW, common differential signal lines DPCM and DMCM, a first transmission driver of which outputs are connected to DPUP and DMUP, a second transmission driver of which outputs are connected to DPDW and DMDW, a first switch circuit which connects the first transmission driver to a logic circuit during upstream connection and connects the second transmission driver to the logic circuit during downstream connection, a second switch circuit which respectively connects DPUP and DMUP to DPCM and DMCM during the upstream connection and respectively connects DPDW and DMDW to DPCM and DMCM during the downstream connection, and a third transmission driver connected to DPCM and DMCM.
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5.发明授权Clock generation circuit, data transfer control device, and electronic instrument 有权时钟发生电路，数据传输控制装置和电子仪器公开(公告)号：US06990597B2
公开(公告)日：2006-01-24
申请号：US09974796
申请日：2001-10-12
IPC分类号： G11B5/35
CPC分类号： H04L7/0337 , G06F1/06 , H03K3/0322 , H03L7/0996 , H03L7/18
摘要： A clock generation circuit capable of generating a high-frequency clock with a simple circuit configuration, together with a data transfer control device and an electronic instrument using the same. The clock generation circuit has: serially-connected inversion circuits IV0 to IV4 in which an output of IV4 is connected to an input of IV0 by a feedback line FL; and buffer circuits BF0 to BF4 which receives outputs from IV0 to IV4. The inversion circuits IV0 to IV4 are disposed along a line LN1 and the buffer circuits BF0 to BF4 are disposed along a line LN2 that is parallel to the feedback line FL but different from LN1. Dummy lines DL0 to DL3 each of which having parasitic capacitance that is equal to that of the feedback line FL are connected to the inversion circuits IV0 to IV3, to equalize the phase differences between clocks CK0 to CK4. The feedback line FL and the dummy lines DL0 to DL3 are disposed in a region between the inversion circuits IV0 to IV4 and the buffer circuits BF0 to BF4. Between which edges of multi-phase clocks an edge of data (data transferred in USB 2.0 HS mode) is located is detected, and a clock selected on the basis of edge detection information is set as a sampling clock.
摘要翻译： 一种能够以简单的电路配置产生高频时钟的时钟发生电路，以及数据传输控制装置和使用该时钟的电子仪器。 时钟发生电路具有：通过反馈线FL将IV4的输出与IV0的输入连接的串联的反相电路IV 0〜IV 4; 以及从IV0至IV4接收输出的缓冲电路BF 0至BF 4。 反相电路IV 0〜IV 4沿着线LN 1配置，缓冲电路BF 0〜BF 4沿着与反馈线FL平行但与LN 1不同的线LN2配置。 具有等于反馈线FL的寄生电容的虚拟线DL 0至DL 3连接到反相电路IV 0至IV 3，以均衡时钟CK 0至CK 4之间的相位差。 反馈线FL和虚线DL 0〜DL 3配置在反相电路IV 0〜IV 4与缓冲电路BF 0〜BF 4之间的区域。 在多相时钟的边缘之间检测数据边缘（以USB 2.0 HS模式传输的数据），并将基于边缘检测信息选择的时钟设置为采样时钟。
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公开(公告)号：US07047332B2
公开(公告)日：2006-05-16
申请号：US10997871
申请日：2004-11-29
申请人： Takuya Ishida , Yoshiyuki Kamihara
发明人： Takuya Ishida , Yoshiyuki Kamihara
IPC分类号： G06F3/00
CPC分类号： G06F13/4018
摘要： A data transfer control device and an electronic instrument which can implement a process to be made on data transmitted and received through a high speed bus on a circuit operating at a low frequency. The data transfer control device has a conversion circuit which converts K-bit width data transferred at a frequency FC1 (in USB 2.0 HS mode) through a bus into data having an L-bit width (L>K) by rearranging, and a processing circuit which receives the L-bit width data from the conversion circuit and carries out a K-bit based process on an L-bit basis at a frequency FC2 lower than FC1. This enables to perform the K-bit based process at the low frequency FC2. Configuration on a transmission end can be implemented in the same manner. The transfer data in the USB 2.0 HS mode is processed on the L-bit basis while the transfer data in the FS mode is processed on the K-bit basis. The present invention is applicable also to the process on data transferred through a bus under the IEEE1394 or SCSI.
摘要翻译： 一种数据传输控制装置和电子仪器，其能够实现在以低频工作的电路上通过高速总线发送和接收的数据进行处理。 数据传送控制装置具有转换电路，其通过总线将通过总线将以频率FC 1（USB 2.0 HS模式）传送的K位宽度数据转换为具有L位宽（L> K）的数据，并且将 处理电路，其从转换电路接收L位宽度数据，并以低于FC 1的频率FC 2在L位的基础上执行基于K位的处理。 这使得能够在低频FC 2下执行基于K位的处理。 传输端的配置可以以相同的方式实现。 USB 2.0 HS模式下的传输数据以L位为基础进行处理，同时以K位为基础处理FS模式下的传送数据。 本发明也适用于通过IEEE1394或SCSI下的总线传送的数据的处理过程。
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7.发明授权Serial/parallel conversion circuit, data transfer control device, and electronic equipment 有权串行/并行转换电路，数据传输控制装置和电子设备公开(公告)号：US06732205B2
公开(公告)日：2004-05-04
申请号：US09977936
申请日：2001-10-17
申请人： Yoshiyuki Kamihara , Takuya Ishida
发明人： Yoshiyuki Kamihara , Takuya Ishida
IPC分类号： G06F1338
CPC分类号： G06F5/06 , H03M9/00 , H04J3/0685
摘要： The present invention provides a serial/parallel conversion circuit that has both a serial/parallel conversion function and a buffer function for absorbing clock frequency differences, together with a data transfer control device and electronic equipment. The serial/parallel conversion circuit (elasticity buffer) comprises a data holding register which holds serial data DIN that is input based on a CLK1 clock (480 MHz) in USB 2.0 HS mode; a determination circuit which determines whether or not held data is valid, by unit of a data cell; and a selector which outputs from the data holding register the data of data cells that have been determined to be valid, based on a CLK2 clock (60 MHz) having a frequency lower than that of CLK1. A data cell in which data of the first bit has been determined to be valid is deemed to be valid in the next CLK2 clock cycle. The determination of whether or not data cells are valid is done in each clock cycle of CLK2, and the output of data in a data cell that is determined not to be valid is made to wait for one clock cycle. A write pulse signal is generated and the data holding register and data status register are operated thereby.
摘要翻译： 本发明提供一种串行/并行转换电路，其具有串行/并行转换功能和用于吸收时钟频率差的缓冲功能，以及数据传输控制装置和电子设备。 串行/并行转换电路（弹性缓冲器）包括数据保持寄存器，其保存在USB 2.0 HS模式下基于CLK1时钟（480MHz）输入的串行数据DIN; 确定电路，其以数据单元为单位确定保持数据是否有效; 以及选择器，其基于具有低于CLK1的频率的CLK2时钟（60MHz）从数据保持寄存器输出已被确定为有效的数据的数据。 其中第一位的数据被确定为有效的数据单元被认为在下一个CLK2时钟周期中有效。 在CLK2的每个时钟周期中确定数据单元是否有效，并且确定不被有效的数据单元中的数据的输出等待一个时钟周期。 产生写脉冲信号，由此操作数据保持寄存器和数据状态寄存器。
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8.发明授权USB data transfer control device including first and second USB device wherein destination information about second device is sent by first device 失效USB数据传输控制设备包括第一和第二USB设备，其中关于第二设备的目的地信息由第一设备发送公开(公告)号：US07359997B2
公开(公告)日：2008-04-15
申请号：US10859082
申请日：2004-06-03
CPC分类号： G06F13/385 , G06F13/4282 , G06F2213/0042
摘要： A transfer controller (or a host controller) issues IN tokens to a plurality of USB devices connected to USB and including first and second USB devices. When data including destination information which specifies the second USB device as a destination has been received in response to an IN token issued to the first USB device, the transfer controller issues an OUT token to the second USB device and transmits the received data from the first USB device to the second USB device. The transfer controller issues an IN token to at least one of the USB devices which has declared itself to be a local area network (LAN) node.
摘要翻译： 转移控制器（或主机控制器）向连接到USB的多个USB设备发出IN令牌，并且包括第一和第二USB设备。 当传送控制器响应于向第一USB设备发出的IN令牌而接收到包括指定作为目的地的第二USB设备的目的地信息的数据时，传送控制器向第二USB设备发出OUT令牌，并且从第一USB设备发送接收到的数据 USB设备到第二个USB设备。 转移控制器向宣布自己是局域网（LAN）节点的至少一个USB设备发出IN令牌。
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9.发明授权Data transfer control device, electronic equipment, and data transfer control method 有权数据传输控制装置，电子设备和数据传输控制方法公开(公告)号：US07051124B2
公开(公告)日：2006-05-23
申请号：US10140834
申请日：2002-05-09
申请人： Takuya Ishida , Yoshiyuki Kamihara
发明人： Takuya Ishida , Yoshiyuki Kamihara
CPC分类号： G06F13/385
摘要： A buffer is provided with a CBW area (a randomly accessible command storage area) and an EP1 area (data storage area set to FIFO), when a CBW and data are allocated as informations to be transferred through one end point EP1. When a phase switches from a USB command phase (command transport) to a data phase (data transport), the information write area is switched from the CBW area to the EP1 area and OUT data transferred from the host to the end point EP1 is written into the EP1 area. The area switches from the CBW area to the EP1 area on condition that an acknowledgment has returned to the host in the command phase. In case of a toggle missing, area switching does not occur even if ACK is returned.
摘要翻译： 当CBW和数据被分配为要通过一个终点EP 1传送的信息时，缓冲器具有CBW区域（随机可访问的命令存储区域）和EP 1区域（设置为FIFO的数据存储区域）。 当相位从USB命令阶段（命令传输）切换到数据相位（数据传输）时，信息写入区域从CBW区域切换到EP 1区域，从主机传输到终端EP 1的OUT数据 被写入EP 1区域。 条件是在命令阶段已经返回到主机的情况下，该区域从CBW区域切换到EP 1区域。 在缺少切换的情况下，即使返回ACK也不会发生区域切换。
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10.发明授权Data transfer control device, electronic equipment, and data transfer control method 有权数据传输控制装置，电子设备和数据传输控制方法公开(公告)号：US07007112B2
公开(公告)日：2006-02-28
申请号：US10140829
申请日：2002-05-09
申请人： Takuya Ishida , Yoshiyuki Kamihara
发明人： Takuya Ishida , Yoshiyuki Kamihara
IPC分类号： G06F3/00
CPC分类号： G06F5/10
摘要： A buffer is provided which includes an EP2 area (a data storage area set to FIFO) and a CSW area (a randomly accessible status storage area), when data and a CSW are allocated as information to be transferred through one end point EP2. When a phase has switched from a USB data phase (data transport) to a status phase (status transport), the information read area is switched from the EP2 area to the CSW area, and IN data to be transferred from the end point EP2 to a host is read from the CSW area. A CSW0 area for success status and a CSW1 area for non-success status are provided, and a status block packet in which is set either success or non-success default information is previously written therein.
摘要翻译： 提供了一种缓冲器，其包括EP2区域（设置为FIFO的数据存储区域）和CSW区域（随机可访问的状态存储区域），当数据和CSW被分配为要通过一个端点EP 2传送的信息时 。 当相位从USB数据相位（数据传输）切换到状态阶段（状态传输）时，信息读取区域从EP2区域切换到CSW区域，并且从端点EP传送IN数据 2从主机读取CSW区域。 提供了用于成功状态的CSW 0区域和用于非成功状态的CSW 1区域，并且其中设置了成功或非成功默认信息的状态块分组被预先写入其中。
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