公开(公告)号：US07545001B2

公开(公告)日：2009-06-09

申请号：US10722218

申请日：2003-11-25

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Kuan Lun Cheng ,  Yi-Ming Sheu

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Kuan Lun Cheng ,  Yi-Ming Sheu

IPC分类号： H01L23/62

CPC分类号： H01L29/7843 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface. A first one of the NMOS and PMOS devices includes one of: (1) first source/drain regions recessed within the surface; and (2) first source/drain regions extending from the surface. A second one of the NMOS and PMOS devices includes one of: (1) second source/drain regions recessed within the surface wherein the first source/drain regions extend from the surface; (2) second source/drain regions extending from the surface wherein the first source/drain regions are recessed within the surface; and (3) second source/drain regions substantially coplanar with the surface.

摘要翻译： 包括位于衬底中的隔离区域的半导体器件，部分地位于衬底的表面上的NMOS器件以及通过隔离区域与NMOS器件隔离并且部分地位于表面上的PMOS器件。 NMOS和PMOS器件中的第一个包括以下之一：（1）凹陷在表面内的第一源极/漏极区域; 和（2）从表面延伸的第一源极/漏极区域。 NMOS和PMOS器件中的第二个包括以下之一：（1）凹陷在表面内的第二源极/漏极区域，其中第一源极/漏极区域从表面延伸; （2）从表面延伸的第二源极/漏极区域，其中第一源极/漏极区域在表面内凹陷; 和（3）基本上与表面共面的第二源极/漏极区域。

公开(公告)号：US06960512B2

公开(公告)日：2005-11-01

申请号：US10602241

申请日：2003-06-24

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang ,  Kuan-Lun Cheng ,  Huan-Tsung Huang

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang ,  Kuan-Lun Cheng ,  Huan-Tsung Huang

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides methods for manufacturing semiconductor devices. In one embodiment, the method includes forming a gate oxide over a substrate and a gate electrode over the gate oxide. The method also includes implanting impurities into the substrate using the gate electrode as an implant mask to form lightly-doped regions in the substrate. The method further includes forming a first spacer adjacent the gate electrode, and implanting impurities into the substrate and through a portion of the lightly-doped regions using the first spacer as an implant mask to form deep source/drain regions in the substrate. The method still further includes forming a second spacer adjacent the first spacer, implanting impurities into the substrate using the second spacer as an implant mask to form a graded source/drain region in the substrate, and removing the second spacer. Also disclosed is a semiconductor device constructed using the techniques disclosed herein.

摘要翻译： 本发明提供半导体器件的制造方法。 在一个实施例中，该方法包括在衬底上形成栅极氧化物，并在栅极氧化物上形成栅电极。 该方法还包括使用栅电极作为注入掩模将杂质植入到衬底中，以在衬底中形成轻掺杂区域。 该方法还包括形成与栅电极相邻的第一间隔物，以及使用第一间隔物作为注入掩模将杂质注入衬底并通过一部分轻掺杂区域，以在衬底中形成深源/漏区。 该方法还包括形成与第一间隔物相邻的第二间隔物，使用第二间隔物作为注入掩模将杂质注入到衬底中，以在衬底中形成渐变源极/漏极区域，以及去除第二间隔物。 还公开了使用本文公开的技术构造的半导体器件。

公开(公告)号：US20050186722A1

公开(公告)日：2005-08-25

申请号：US10786643

申请日：2004-02-25

申请人： Kuan-Lun Cheng ,  Huan-Tsung Huang ,  Shui-Ming Cheng ,  Yin-Pin Wang ,  Ka-Hing Fung

发明人： Kuan-Lun Cheng ,  Huan-Tsung Huang ,  Shui-Ming Cheng ,  Yin-Pin Wang ,  Ka-Hing Fung

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/31155 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/7842 ,  H01L29/7843

摘要： Stress in a silicon nitride contact etch stop layer on a CMOS structure having NMOS and PMOS devices is selectively relieved by selective implantation of oxygen-containing or carbon-containing ions resulting in there being no tensile stress in areas of the layer above the PMOS devices and no compressive stress in areas of the layer above the NMOS devices.

摘要翻译： 在具有NMOS和PMOS器件的CMOS结构上的氮化硅接触蚀刻停止层中的应力通过选择性注入含氧或含碳离子来选择性地释放，导致在PMOS器件上方的层的区域中不存在拉伸应力， 在NMOS器件上方的层的区域中没有压应力。

公开(公告)号：US20050110082A1

公开(公告)日：2005-05-26

申请号：US10722218

申请日：2003-11-25

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Kuan Cheng ,  Yi-Ming Sheu

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Kuan Cheng ,  Yi-Ming Sheu

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/76

CPC分类号： H01L29/7843 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface. A first one of the NMOS and PMOS devices includes one of: (1) first source/drain regions recessed within the surface; and (2) first source/drain regions extending from the surface. A second one of the NMOS and PMOS devices includes one of: (1) second source/drain regions recessed within the surface wherein the first source/drain regions extend from the surface; (2) second source/drain regions extending from the surface wherein the first source/drain regions are recessed within the surface; and (3) second source/drain regions substantially coplanar with the surface.

摘要翻译： 包括位于衬底中的隔离区域的半导体器件，部分地位于衬底的表面上的NMOS器件以及通过隔离区域与NMOS器件隔离并且部分地位于表面上的PMOS器件。 NMOS和PMOS器件中的第一个包括以下之一：（1）凹陷在表面内的第一源极/漏极区域; 和（2）从表面延伸的第一源极/漏极区域。 NMOS和PMOS器件中的第二个包括以下之一：（1）凹陷在表面内的第二源极/漏极区域，其中第一源极/漏极区域从表面延伸; （2）从表面延伸的第二源极/漏极区域，其中第一源极/漏极区域在表面内凹陷; 和（3）基本上与表面共面的第二源极/漏极区域。

公开(公告)号：US07220630B2

公开(公告)日：2007-05-22

申请号：US10851377

申请日：2004-05-21

申请人： Kaun-Lun Cheng ,  Shui-Ming Cheng ,  Yu-Yuan Yao ,  Ka-Hing Fung ,  Sun-Jay Chang

发明人： Kaun-Lun Cheng ,  Shui-Ming Cheng ,  Yu-Yuan Yao ,  Ka-Hing Fung ,  Sun-Jay Chang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

摘要： A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a stress selected from the group consisting of compressive and tensile on the first and second FET devices; and, removing a thickness portion of the strained layer over one of the first and second FET devices to improve charge carrier mobility.

摘要翻译： 一种具有改善的电荷载流子迁移率的应变沟道MOSFET器件及其形成方法，所述方法包括：在衬底上提供具有与第一极性相反的第一极性和第二极性的第一和第二FET器件; 形成在第一和第二FET器件上具有选自压缩和拉伸的应力的应变层; 并且通过所述第一和第二FET器件中的一个去除所述应变层的厚度部分以改善电荷载流子迁移率。

公开(公告)号：US20050260810A1

公开(公告)日：2005-11-24

申请号：US10851377

申请日：2004-05-21

申请人： Kaun-Lun Cheng ,  Shui-Ming Cheng ,  Yu-Yuan Yao ,  Ka-Hing Fung ,  Sun-Jay Chang

发明人： Kaun-Lun Cheng ,  Shui-Ming Cheng ,  Yu-Yuan Yao ,  Ka-Hing Fung ,  Sun-Jay Chang

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

摘要： A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a stress selected from the group consisting of compressive and tensile on the first and second FET devices; and, removing a thickness portion of the strained layer over one of the first and second FET devices to improve charge carrier mobility.

摘要翻译： 一种具有改善的电荷载流子迁移率的应变沟道MOSFET器件及其形成方法，所述方法包括：在衬底上提供具有与第一极性相反的第一极性和第二极性的第一和第二FET器件; 形成在第一和第二FET器件上具有选自压缩和拉伸的应力的应变层; 并且通过所述第一和第二FET器件中的一个去除所述应变层的厚度部分以改善电荷载流子迁移率。

公开(公告)号：US20050145881A1

公开(公告)日：2005-07-07

申请号：US10749080

申请日：2003-12-30

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

IPC分类号： H01L27/01 ,  H01L29/08 ,  H01L29/772 ,  H01L29/78 ,  H01L31/0328

CPC分类号： H01L29/0847 ,  H01L29/7833

摘要： Field effect transistors having reduced reverse body effects and reduced parasitic junction capacitance and a method of manufacture. The FET's comprise source/drain region pairs formed in said bulk silicon, each pair separated by a channel region. The depletion region associated with each of the source/drain regions of a pair are fully merged by selective ion implantation. A gate electrode is formed or deposited over the channel region of each FET in the normal manner.

公开(公告)号：US20050133831A1

公开(公告)日：2005-06-23

申请号：US10743985

申请日：2003-12-22

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/76 ,  H01L21/425 ,  H01L27/01 ,  H01L31/0392 ,  H01L31/062

CPC分类号： H01L29/66772 ,  H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78615

摘要： An SOI device (100) has a gate electrode with one or more additional gate regions (120), and oxygen or halogen ions (128) under the additional gate regions (120). The oxygen or halogen ions (128) form thicker gate oxide regions or shallow trench isolation regions.

摘要翻译： SOI器件（100）具有在附加栅极区域（120）下方具有一个或多个附加栅极区域（120）的栅极电极和氧或卤素离子（128）。 氧或卤素离子（128）形成较厚的栅极氧化物区域或浅沟槽隔离区域。

公开(公告)号：US07453121B2

公开(公告)日：2008-11-18

申请号：US10743985

申请日：2003-12-22

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

IPC分类号： H01L21/00

CPC分类号： H01L29/66772 ,  H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78615

摘要： An SOI device (100) has a gate electrode with one or more additional gate regions (120), and oxygen or halogen ions (128) under the additional gate regions (120). The oxygen or halogen ions (128) form thicker gate oxide regions or shallow trench isolation regions.

摘要翻译： SOI器件（100）具有在附加栅极区域（120）下方具有一个或多个附加栅极区域（120）的栅极电极和氧或卤素离子（128）。 氧或卤素离子（128）形成较厚的栅极氧化物区域或浅沟槽隔离区域。

公开(公告)号：US20050275022A1

公开(公告)日：2005-12-15

申请号：US11204827

申请日：2005-08-16

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

IPC分类号： H01L27/01 ,  H01L29/08 ,  H01L29/772 ,  H01L29/78 ,  H01L31/0328

CPC分类号： H01L29/0847 ,  H01L29/7833

摘要： Field effect transistors having reduced reverse body effects and reduced parasitic junction capacitance and a method of manufacture. The FET's comprise source/drain region pairs formed in said bulk silicon, each pair separated by a channel region. The depletion region associated with each of the source/drain regions of a pair are fully merged by selective ion implantation. A gate electrode is formed or deposited over the channel region of each FET in the normal manner.

摘要翻译： 具有减小的反体效应和减小的寄生结电容的场效应晶体管及其制造方法。 FET包括形成在所述体硅中的源/漏区对，每对由沟道区分隔。 与一对的源极/漏极区域中的每一个相关联的耗尽区域通过选择性离子注入完全合并。 栅极电极以正常方式形成或沉积在每个FET的沟道区上。