公开(公告)号：US07883979B2

公开(公告)日：2011-02-08

申请号：US10973966

申请日：2004-10-26

申请人： Hung-Wei Chen ,  Zhong Tang Xuan ,  Shui-Ming Cheng ,  Sheng-Da Liu

发明人： Hung-Wei Chen ,  Zhong Tang Xuan ,  Shui-Ming Cheng ,  Sheng-Da Liu

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78621 ,  H01L29/78684 ,  Y10S438/933

摘要： A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated extending a second depth within the substrate, the second depth not equal to the first depth.

摘要翻译： 半导体器件包括衬底，位于衬底上的第一器件，第一器件包括源和漏极，每个源极和漏极都位于衬底内延伸第一深度，第二器件位于衬底上，第二器件包括源极和 一个排水口，每个位于在衬底内延伸第二深度，第二深度不等于第一深度。

公开(公告)号：US07453121B2

公开(公告)日：2008-11-18

申请号：US10743985

申请日：2003-12-22

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

IPC分类号： H01L21/00

CPC分类号： H01L29/66772 ,  H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78615

摘要： An SOI device (100) has a gate electrode with one or more additional gate regions (120), and oxygen or halogen ions (128) under the additional gate regions (120). The oxygen or halogen ions (128) form thicker gate oxide regions or shallow trench isolation regions.

摘要翻译： SOI器件（100）具有在附加栅极区域（120）下方具有一个或多个附加栅极区域（120）的栅极电极和氧或卤素离子（128）。 氧或卤素离子（128）形成较厚的栅极氧化物区域或浅沟槽隔离区域。

公开(公告)号：US20070190731A1

公开(公告)日：2007-08-16

申请号：US11353309

申请日：2006-02-14

申请人： Hao-Yu Chen ,  Shui-Ming Cheng

发明人： Hao-Yu Chen ,  Shui-Ming Cheng

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.

摘要翻译： 提供了一种用于半导体器件的扩散层。 根据本发明的实施例，诸如晶体管的半导体器件包括被扩散阻挡层包围的掺杂区域。 扩散阻挡层可以通过衬底的凹陷区域和注入氟或碳离子形成。 可以在凹陷区域中的扩散阻挡层上外延生长硅层。 此后，可以用半导体或半导体合金材料填充和掺杂凹陷区域。 在一个实施例中，选择诸如硅碳的半导体合金材料以在NMOS器件的沟道区域中引起拉伸应力，并且选择诸如硅锗的半导体合金材料以在 沟道区域。

公开(公告)号：US20060086987A1

公开(公告)日：2006-04-27

申请号：US10973966

申请日：2004-10-26

申请人： Hung-Wei Chen ,  Zhong Xuan ,  Shui-Ming Cheng ,  Sheng-Da Liu

发明人： Hung-Wei Chen ,  Zhong Xuan ,  Shui-Ming Cheng ,  Sheng-Da Liu

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78621 ,  H01L29/78684 ,  Y10S438/933

摘要： A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated extending a second depth within the substrate, the second depth not equal to the first depth.

摘要翻译： 半导体器件包括衬底，位于衬底上的第一器件，第一器件包括源和漏极，每个源极和漏极都位于衬底内延伸第一深度，第二器件位于衬底上，第二器件包括源极和 一个排水口，每个位于在衬底内延伸第二深度，第二深度不等于第一深度。

公开(公告)号：US20050275022A1

公开(公告)日：2005-12-15

申请号：US11204827

申请日：2005-08-16

申请人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

发明人： Shui-Ming Cheng ,  Ka-Hing Fung ,  Yin-Pin Wang

IPC分类号： H01L27/01 ,  H01L29/08 ,  H01L29/772 ,  H01L29/78 ,  H01L31/0328

CPC分类号： H01L29/0847 ,  H01L29/7833

摘要： Field effect transistors having reduced reverse body effects and reduced parasitic junction capacitance and a method of manufacture. The FET's comprise source/drain region pairs formed in said bulk silicon, each pair separated by a channel region. The depletion region associated with each of the source/drain regions of a pair are fully merged by selective ion implantation. A gate electrode is formed or deposited over the channel region of each FET in the normal manner.

摘要翻译： 具有减小的反体效应和减小的寄生结电容的场效应晶体管及其制造方法。 FET包括形成在所述体硅中的源/漏区对，每对由沟道区分隔。 与一对的源极/漏极区域中的每一个相关联的耗尽区域通过选择性离子注入完全合并。 栅极电极以正常方式形成或沉积在每个FET的沟道区上。

公开(公告)号：US20050186722A1

公开(公告)日：2005-08-25

申请号：US10786643

申请日：2004-02-25

申请人： Kuan-Lun Cheng ,  Huan-Tsung Huang ,  Shui-Ming Cheng ,  Yin-Pin Wang ,  Ka-Hing Fung

发明人： Kuan-Lun Cheng ,  Huan-Tsung Huang ,  Shui-Ming Cheng ,  Yin-Pin Wang ,  Ka-Hing Fung

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/31155 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/7842 ,  H01L29/7843

摘要： Stress in a silicon nitride contact etch stop layer on a CMOS structure having NMOS and PMOS devices is selectively relieved by selective implantation of oxygen-containing or carbon-containing ions resulting in there being no tensile stress in areas of the layer above the PMOS devices and no compressive stress in areas of the layer above the NMOS devices.

摘要翻译： 在具有NMOS和PMOS器件的CMOS结构上的氮化硅接触蚀刻停止层中的应力通过选择性注入含氧或含碳离子来选择性地释放，导致在PMOS器件上方的层的区域中不存在拉伸应力， 在NMOS器件上方的层的区域中没有压应力。

公开(公告)号：US07348248B2

公开(公告)日：2008-03-25

申请号：US11179232

申请日：2005-07-12

申请人： Shui-Ming Cheng

发明人： Shui-Ming Cheng

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim gate spacer along a side of the gate electrode, and a source/drain region substantially aligned with an edge of the slim gate spacer. The source/drain region includes a first implantation region having an overlap with the gate electrode, a second implantation region further away from the channel region than the first implantation region, and a third implantation region further away from the channel region than the second implantation region. The source/drain region preferably further comprises an epitaxy region spaced apart from the slim gate spacer.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括在衬底上的栅极电介质，栅极电介质上的栅极电极，沿着栅极电极的侧面的细长栅极间隔物，以及基本上与细长栅极间隔物的边缘对准的源极/漏极区域。 源极/漏极区域包括与栅电极重叠的第一注入区域，比第一注入区域更远离沟道区域的第二注入区域和比第二注入区域更远离沟道区域的第三注入区域 。 源极/漏极区域优选地还包括与薄的栅极间隔物隔开的外延区域。

公开(公告)号：US20080061379A1

公开(公告)日：2008-03-13

申请号：US11518046

申请日：2006-09-08

申请人： Hao-Yu Chen ,  Shui-Ming Cheng ,  Ken-Ichi Goto

发明人： Hao-Yu Chen ,  Shui-Ming Cheng ,  Ken-Ichi Goto

IPC分类号： H01L29/772

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： An MOS device includes a gate stack overlying a semiconductor substrate and a graded source/drain region adjacent to the gate stack. The graded source/drain region includes a first grade having a first depth, a second grade spaced further apart from a channel region than the first grade, and a third grade spaced further apart from the channel region than the second grade. The depth of the second grade is between the respective depths of the first and the third grades. The MOS device further includes a silicide region on a top surface of the source/drain region wherein the silicide region has an inner edge substantially aligned with an inner edge of the third grade, and a graded gate spacer comprising an inner portion on a sidewall of the gate stack and an outer portion on a sidewall of the inner portion.

摘要翻译： MOS器件包括覆盖半导体衬底的栅极堆叠和与栅极堆叠相邻的渐变源极/漏极区域。 分级源极/漏极区域包括具有第一深度的第一等级，与沟道区间比第一等级更远离的第二等级，以及与第二等级相比更远离沟道区的三级。 二年级的深度在第一和第三等级的相应深度之间。 MOS器件还包括在源极/漏极区域的顶表面上的硅化物区域，其中硅化物区域具有基本上与三级内部边缘对准的内边缘，以及梯度栅极间隔件，其包括在侧壁上的内部部分 栅极堆叠和内部部分的侧壁上的外部部分。

公开(公告)号：US07220630B2

公开(公告)日：2007-05-22

申请号：US10851377

申请日：2004-05-21

申请人： Kaun-Lun Cheng ,  Shui-Ming Cheng ,  Yu-Yuan Yao ,  Ka-Hing Fung ,  Sun-Jay Chang

发明人： Kaun-Lun Cheng ,  Shui-Ming Cheng ,  Yu-Yuan Yao ,  Ka-Hing Fung ,  Sun-Jay Chang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

摘要： A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a stress selected from the group consisting of compressive and tensile on the first and second FET devices; and, removing a thickness portion of the strained layer over one of the first and second FET devices to improve charge carrier mobility.

摘要翻译： 一种具有改善的电荷载流子迁移率的应变沟道MOSFET器件及其形成方法，所述方法包括：在衬底上提供具有与第一极性相反的第一极性和第二极性的第一和第二FET器件; 形成在第一和第二FET器件上具有选自压缩和拉伸的应力的应变层; 并且通过所述第一和第二FET器件中的一个去除所述应变层的厚度部分以改善电荷载流子迁移率。

公开(公告)号：US20050148148A1

公开(公告)日：2005-07-07

申请号：US11059956

申请日：2005-02-17

申请人： Shui-Ming Cheng

发明人： Shui-Ming Cheng

IPC分类号： H01L21/8234 ,  H01L29/745 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L21/823418 ,  H01L21/823481

摘要： A method of forming a source/drain having a reduced junction capacitance and a transistor employing the same. In one embodiment, the method of forming the source/drain includes forming a recess in a substrate adjacent a gate of the transistor and forming a deep doped region below a bottom surface of the recess. The method also includes epitaxially growing a semiconductor material within the recess and forming a lightly doped drain region adjacent the gate.