公开(公告)号：US20080164556A1

公开(公告)日：2008-07-10

申请号：US11862585

申请日：2007-09-27

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Shuji Tanaka

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Shuji Tanaka

IPC分类号： H01L29/866

CPC分类号： H01L27/0788 ,  H01L27/0255 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/47 ,  H01L29/866 ,  H01L29/872

摘要： There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes P-type first and second anode diffusion layers formed in an N-type epitaxial layer, N-type cathode diffusion layers formed in the epitaxial layer, a P-type third anode diffusion layer formed in the epitaxial layer so as to surround the first and second anode diffusion layers and to extend toward the cathode diffusion layers, and a Schottky barrier metal layer formed on the first and second anode diffusion layers.

摘要翻译： 在肖特基势垒二极管中存在反向漏电流变得过大的问题。 本发明的半导体器件包括形成在N型外延层中的P型第一和第二阳极扩散层，在外延层中形成的N型阴极扩散层，形成在外延层中的P型第三阳极扩散层 以便围绕第一和第二阳极扩散层并朝向阴极扩散层延伸，以及形成在第一和第二阳极扩散层上的肖特基势垒金属层。

公开(公告)号：US08552469B2

公开(公告)日：2013-10-08

申请号：US11862585

申请日：2007-09-27

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Shuji Tanaka

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Shuji Tanaka

IPC分类号： H01L29/66 ,  H01L29/47

CPC分类号： H01L27/0788 ,  H01L27/0255 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/47 ,  H01L29/866 ,  H01L29/872

摘要： There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes P-type first and second anode diffusion layers formed in an N-type epitaxial layer, N-type cathode diffusion layers formed in the epitaxial layer, a P-type third anode diffusion layer formed in the epitaxial layer so as to surround the first and second anode diffusion layers and to extend toward the cathode diffusion layers, and a Schottky barrier metal layer formed on the first and second anode diffusion layers.

摘要翻译： 在肖特基势垒二极管中存在反向漏电流变得过大的问题。 本发明的半导体器件包括形成在N型外延层中的P型第一和第二阳极扩散层，在外延层中形成的N型阴极扩散层，形成在外延层中的P型第三阳极扩散层 以便围绕第一和第二阳极扩散层并朝向阴极扩散层延伸，以及形成在第一和第二阳极扩散层上的肖特基势垒金属层。

公开(公告)号：US07737523B2

公开(公告)日：2010-06-15

申请号：US11395599

申请日：2006-03-30

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC分类号： H01L29/93

CPC分类号： H01L29/872 ,  H01L29/866

摘要： In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, a P-type diffusion layer is formed to be connected to a P-type diffusion layer and is extended to a cathode region. A metal layer to which an anode electrode is applied is formed above the P-type diffusion layer, thereby making it possible to obtain a field plate effect. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

摘要翻译： 在本发明的半导体器件中，在形成在基板上的外延层上形成用于保护器件的保护二极管。 在外延层的表面上形成肖特基势垒金属层，在肖特基势垒金属层的端部的下部形成P型扩散层。 然后，形成P型扩散层以连接到P型扩散层并延伸到阴极区。 在P型扩散层的上方形成有施加了阳极电极的金属层，能够得到场板效应。 这种结构减小了耗尽层的曲率的大的变化，从而提高了保护二极管的耐电压特性。

公开(公告)号：US20060244091A1

公开(公告)日：2006-11-02

申请号：US11395890

申请日：2006-03-30

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC分类号： H01L31/07

CPC分类号： H01L29/872 ,  H01L27/0255 ,  H01L29/0692 ,  H01L29/8611 ,  H01L29/868

摘要： In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, P-type diffusion layers are formed in a floating state closer to a cathode region side than the P-type diffusion layer, and are capacitively coupled with a metal layer to which an anode potential is applied. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

摘要翻译： 在本发明的半导体器件中，在形成在基板上的外延层上形成用于保护器件的保护二极管。 在外延层的表面上形成肖特基势垒金属层，在肖特基势垒金属层的端部的下部形成P型扩散层。 然后，P型扩散层形成为比P型扩散层更靠近阴极区域的浮置状态，并且与施加有阳极电位的金属层电容耦合。 这种结构减小了耗尽层的曲率的大的变化，从而提高了保护二极管的耐电压特性。

公开(公告)号：US20070057321A1

公开(公告)日：2007-03-15

申请号：US11516733

申请日：2006-09-07

申请人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shigeaki Okawa

发明人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shigeaki Okawa

IPC分类号： H01L29/76 ,  H01L21/76

CPC分类号： H01L29/0696 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/7816

摘要： In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.

摘要翻译： 在本发明的半导体器件中，MOS晶体管被设置为椭圆形。 分别使用椭圆形状的线性区域作为有效区域，椭圆形状的圆形区域分别用作非活性区域。 在每个非活性区域中，形成P型扩散层以与圆形重合。 另一个P型扩散层形成在一个非活性区域的一部分中。 这些P型扩散层形成为浮动扩散层，电容耦合到绝缘层上的金属层，并且呈现分别施加预定电位的状态。 这种结构使得有可能保持有源区的电流性能，同时提高无源区的耐压特性。

公开(公告)号：US20060220099A1

公开(公告)日：2006-10-05

申请号：US11391166

申请日：2006-03-27

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC分类号： H01L29/788

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41725 ,  H01L29/42368 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a conventional semiconductor device, there has been a problem that, in a region where a wiring layer to which a high electric potential is applied traverses a top surface of an isolation region, the withstand voltage is deteriorated. In a semiconductor device of the present invention, an epitaxial layer is deposited on a substrate, and an LDMOSFET is formed in one region divided by an isolation region. In a region where a wiring layer connected to a drain electrode traverses a top surface of the isolation region, a conductive plate having a ground electric potential and another conductive plate in a floating state are formed under the wiring layer. With this structure, electric field is reduced in the vicinity of the isolation region under the wiring layer, whereby a withstand voltage of the LDMOSFET is increased.

摘要翻译： 在现有的半导体装置中，存在如下问题：在施加高电位的布线层横越隔离区域的上表面的区域中，耐电压劣化。 在本发明的半导体器件中，在衬底上沉积外延层，并且在由隔离区域划分的一个区域中形成LDMOSFET。 在与漏电极连接的布线层穿过隔离区域的上表面的区域中，在布线层的下方形成具有接地电位的导电板和浮置状态的另一导电板。 利用这种结构，在布线层下面的隔离区附近减小了电场，从而提高了LDMOSFET的耐受电压。

公开(公告)号：US07652307B2

公开(公告)日：2010-01-26

申请号：US11516733

申请日：2006-09-07

申请人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shigeaki Okawa

发明人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shigeaki Okawa

IPC分类号： H01L29/00

CPC分类号： H01L29/0696 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/7816

摘要： In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.

摘要翻译： 在本发明的半导体器件中，MOS晶体管被设置为椭圆形。 分别使用椭圆形状的线性区域作为有效区域，椭圆形状的圆形区域分别用作非活性区域。 在每个非活性区域中，形成P型扩散层以与圆形重合。 另一个P型扩散层形成在一个非活性区域的一部分中。 这些P型扩散层形成为浮动扩散层，电容耦合到绝缘层上的金属层，并且呈现分别施加预定电位的状态。 这种结构使得有可能保持有源区的电流性能，同时提高无源区的耐压特性。

公开(公告)号：US20060220166A1

公开(公告)日：2006-10-05

申请号：US11395599

申请日：2006-03-30

申请人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

发明人： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC分类号： H01L29/861

CPC分类号： H01L29/872 ,  H01L29/866

摘要： In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, a P-type diffusion layer is formed to be connected to a P-type diffusion layer and is extended to a cathode region. A metal layer to which an anode electrode is applied is formed above the P-type diffusion layer, thereby making it possible to obtain a field plate effect. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

摘要翻译： 在本发明的半导体器件中，在形成在基板上的外延层上形成用于保护器件的保护二极管。 在外延层的表面上形成肖特基势垒金属层，在肖特基势垒金属层的端部的下部形成P型扩散层。 然后，形成P型扩散层以连接到P型扩散层并延伸到阴极区。 在P型扩散层的上方形成有施加了阳极电极的金属层，能够得到场板效应。 这种结构减小了耗尽层的曲率的大的变化，从而提高了保护二极管的耐电压特性。

公开(公告)号：US08558307B2

公开(公告)日：2013-10-15

申请号：US11958531

申请日：2007-12-18

申请人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shuji Tanaka

发明人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shuji Tanaka

IPC分类号： H01L29/66

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835

摘要： It is desirable to reduce chip area, lower on resistance and improve electric current driving capacity of a DMOS transistor in a semiconductor device with a DMOS transistor. On the surface of an N type epitaxial layer, a P+W layer of the opposite conductivity type (P type) is disposed and a DMOS transistor is formed in the P+W layer. The epitaxial layer and a drain region are insulated by the P+W layer. Therefore, it is possible to form both the DMOS transistor and other device element in a single confined region surrounded by an isolation layer. An N type FN layer is disposed on the surface region of the P+W layer beneath the gate electrode. An N+D layer, which is adjacent to the edge of the gate electrode of the drain layer side, is also formed. P type impurity layers (a P+D layer and a FP layer), which are located below the drain layer, are disposed beneath the contact region of the drain layer.

摘要翻译： 期望在具有DMOS晶体管的半导体器件中减小芯片面积，降低导通电阻并提高DMOS晶体管的电流驱动能力。 在N型外延层的表面上设置相反导电型（P型）的P + W层，在P + W层形成DMOS晶体管。 外延层和漏极区由P + W层绝缘。 因此，可以在由隔离层包围的单个限制区域内形成DMOS晶体管和其它器件元件。 N型FN层设置在栅电极下面的P + W层的表面区域上。 还形成了与漏极层侧的栅电极的边缘相邻的N + D层。 位于漏极层下方的P型杂质层（P + D层和FP层）设置在漏极层的接触区域的下方。

公开(公告)号：US07649224B2

公开(公告)日：2010-01-19

申请号：US11956097

申请日：2007-12-13

申请人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shuji Tanaka

发明人： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shuji Tanaka

IPC分类号： H01L23/62

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404

摘要： This invention is directed to offer a MOS transistor that has a high source-drain breakdown BVds, a low on resistance and a high electric current driving capacity. On resistance is lowered by forming an N well layer for lowering on resistance in the drift region. The N well layer is disposed beneath the gate electrode and away from the N well layer with a certain space between them. This space ensures the withstand voltage at the edge of the gate electrode of the drain layer side. Also, the N well layer is formed on the surface of an epitaxial layer in the region that includes a P+L layer. The edge of the N well layer of the drain layer side is located near the edge of the P+L layer of the drain layer side and away from the N well layer. This space makes the expansion of depletion layer from the P+L layer easier, further improving the withstand voltage.

摘要翻译： 本发明旨在提供一种具有高的源极 - 漏极击穿BVds，低导通电阻和高电流驱动能力的MOS晶体管。 通过在漂移区域中形成用于降低导通电阻的N阱层来降低电阻。 N阱层设置在栅电极下方并且远离N阱层之间具有一定的间隔。 该空间确保漏极层侧的栅电极的边缘处的耐受电压。 此外，在包括P + L层的区域中，在外延层的表面上形成N阱层。 漏层侧的N阱层的边缘位于漏极层侧的P + L层的边缘附近并远离N阱层。 该空间使得P + L层的耗尽层膨胀更加容易，进一步提高了耐压。