公开(公告)号：US06207518B1

公开(公告)日：2001-03-27

申请号：US09512524

申请日：2000-02-24

申请人： Yumiko Akaishi ,  Shuichi Kikuchi

发明人： Yumiko Akaishi ,  Shuichi Kikuchi

IPC分类号： H01L21336

CPC分类号： H01L29/0847 ,  H01L29/66659 ,  H01L29/7835

摘要： Disclosed is a method of manufacturing a semiconductor device which includes a source region, a channel region, a drain region, a gate electrode formed on the channel region through a gate insulating film 6 and a drift region (N− layer 22) formed between the channel region and the drain region, wherein the process of forming the drift region (N− layer) comprises the steps of: ion-implanting and diffusing at least two kinds of second conduction type impurities (e.g. phosphorus and arsenic ions) having different diffusion coefficients in a P-type well region 21; ion-implanting at least one kind first conduction type impurities (e.g. boron ions) having a diffusion coefficient substantially equal to or larger than that of at least one of said second conduction type impurities (e.g. phosphorus); and diffusing the first conduction type impurities after the gate insulating film 6 has been formed.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件包括通过栅极绝缘膜6形成在沟道区上的源极区，沟道区，漏极区，栅电极以及形成在栅极绝缘膜6之间的漂移区（N层22） 沟道区域和漏极区域，其中形成漂移区域（N层）的工艺包括以下步骤：离子注入和扩散具有不同扩散系数的至少两种第二导电类型杂质（例如磷和砷离子） 在P型井区域21中; 离子注入具有基本上等于或大于所述第二导电类型杂质（例如磷）中的至少一种的扩散系数的至少一种第一导电类型杂质（例如硼离子）; 并且在形成栅极绝缘膜6之后扩散第一导电型杂质。

公开(公告)号：US06614075B2

公开(公告)日：2003-09-02

申请号：US09852540

申请日：2001-05-10

申请人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

发明人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

IPC分类号： H01L2978

CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L29/1095 ,  H01L29/7835

摘要： A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.

摘要翻译： 半导体器件包括源极区域4，沟道区域8，漏极区域5和栅极电极，其被图案化，使得其侧壁是锥形的，以朝向顶部更窄。 在沟道区域8和漏极区域5之间形成漂移区域22，以便在栅极电极7A（第一N-层22A）的下方并且在漏极区域5（第二N-层22B）附近的深处。 该配置有助于提高耐压并降低半导体器件的“导通”电阻。

公开(公告)号：US06599782B1

公开(公告)日：2003-07-29

申请号：US09716782

申请日：2000-11-20

申请人： Shuichi Kikuchi ,  Yumiko Akaishi ,  Takuya Suzuki

发明人： Shuichi Kikuchi ,  Yumiko Akaishi ,  Takuya Suzuki

IPC分类号： H01L21339

CPC分类号： H01L29/66659 ,  H01L29/0886 ,  H01L29/7835

摘要： To enhance the withstand voltage of an LD MOS transistor, a method of fabricating a semiconductor device according to the invention is characterized in that a process for forming a drift region is composed of a step for implanting phosphorus ions and arsenic ions different in a diffusion coefficient into the superficial layer of a substrate, a step for forming a selective oxide film (a first gate insulating film) 9A and an element isolation film 9B by selective oxidation and diffusing the phosphorus ions and the arsenic ions and a step for implanting and diffusing boron ions, and in that in the step for forming the selective oxide film 9A and the element isolation film 9B by selective oxidation in a state in which an oxide film and a polycrystalline silicon film are laminated on the substrate, only a drift region formation region is selectively oxidized in a state in which the polycrystalline silicon film is removed.

摘要翻译： 为了提高LD MOS晶体管的耐受电压，根据本发明的制造半导体器件的方法的特征在于，用于形成漂移区域的工艺由用于注入扩散系数不同的磷离子和砷离子的步骤 进入基板的表层，通过选择性氧化和扩散磷离子和砷离子形成选择性氧化物膜（第一栅极绝缘膜）9A和元件隔离膜9B的步骤和用于注入和扩散硼的步骤 离子，并且在用于在氧化膜和多晶硅膜层叠在基板上的状态下通过选择性氧化形成选择性氧化物膜9A和元件隔离膜9B的步骤中，仅漂移区形成区域为 在去除多晶硅膜的状态下选择性氧化。

公开(公告)号：US06897525B1

公开(公告)日：2005-05-24

申请号：US09444819

申请日：1999-11-22

申请人： Shuichi Kikuchi ,  Yumiko Akaishi

发明人： Shuichi Kikuchi ,  Yumiko Akaishi

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/148 ,  H01L29/08 ,  H01L29/68 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66659 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1463 ,  H01L29/0847 ,  H01L29/7833 ,  H01L29/7835

摘要： In order to improve the characteristics of the high breakdown voltage MOS, a semiconductor device of the present invention is characterized in that an LDMOS transistor, which comprises a source region 4, a channel region 8, and a drain region 5, and a gate electrode 7 formed on the channel region 8, and a drift region formed between the channel region 8 and the drain region 5, wherein an N−-type low concentration layer 22 serving as the drift region is formed shallowly at least below the gate electrode 7 (first N−-type layer 22A) but formed deeply in a neighborhood of the drain region 5 (second N−-type layer 22B).

摘要翻译： 为了提高高击穿电压MOS的特性，本发明的半导体器件的特征在于，包括源极区域4，沟道区域8和漏极区域5的LDMOS晶体管和栅极电极 7，形成在沟道区域8和漏极区域5之间的​​漂移区域，其中用作漂移区域的N + - 低浓度层22浅浅地形成 至少在栅极电极7（第一N +型层22 A）的下方形成，但是深深地形成在漏极区域5的附近（第二N + - 层22B ）。

公开(公告)号：US06255154B1

公开(公告)日：2001-07-03

申请号：US09512520

申请日：2000-02-24

申请人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

发明人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

IPC分类号： H01L218238

CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L29/1095 ,  H01L29/7835

摘要： A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.

摘要翻译： 半导体器件包括源极区域4，沟道区域8，漏极区域5和栅极电极，其被图案化，使得其侧壁成锥形以朝向顶部更窄。 在沟道区域8和漏极区域5之间形成漂移区域22，以便在栅极电极7A（第一N-层22A）的下方并且在漏极区域5（第二N-层22B）附近的深处。 该配置有助于提高耐压并降低半导体器件的“导通”电阻。