公开(公告)号：US06614075B2

公开(公告)日：2003-09-02

申请号：US09852540

申请日：2001-05-10

申请人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

发明人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

IPC分类号： H01L2978

CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L29/1095 ,  H01L29/7835

摘要： A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.

摘要翻译： 半导体器件包括源极区域4，沟道区域8，漏极区域5和栅极电极，其被图案化，使得其侧壁是锥形的，以朝向顶部更窄。 在沟道区域8和漏极区域5之间形成漂移区域22，以便在栅极电极7A（第一N-层22A）的下方并且在漏极区域5（第二N-层22B）附近的深处。 该配置有助于提高耐压并降低半导体器件的“导通”电阻。

公开(公告)号：US06599782B1

公开(公告)日：2003-07-29

申请号：US09716782

申请日：2000-11-20

申请人： Shuichi Kikuchi ,  Yumiko Akaishi ,  Takuya Suzuki

发明人： Shuichi Kikuchi ,  Yumiko Akaishi ,  Takuya Suzuki

IPC分类号： H01L21339

CPC分类号： H01L29/66659 ,  H01L29/0886 ,  H01L29/7835

摘要： To enhance the withstand voltage of an LD MOS transistor, a method of fabricating a semiconductor device according to the invention is characterized in that a process for forming a drift region is composed of a step for implanting phosphorus ions and arsenic ions different in a diffusion coefficient into the superficial layer of a substrate, a step for forming a selective oxide film (a first gate insulating film) 9A and an element isolation film 9B by selective oxidation and diffusing the phosphorus ions and the arsenic ions and a step for implanting and diffusing boron ions, and in that in the step for forming the selective oxide film 9A and the element isolation film 9B by selective oxidation in a state in which an oxide film and a polycrystalline silicon film are laminated on the substrate, only a drift region formation region is selectively oxidized in a state in which the polycrystalline silicon film is removed.

摘要翻译： 为了提高LD MOS晶体管的耐受电压，根据本发明的制造半导体器件的方法的特征在于，用于形成漂移区域的工艺由用于注入扩散系数不同的磷离子和砷离子的步骤 进入基板的表层，通过选择性氧化和扩散磷离子和砷离子形成选择性氧化物膜（第一栅极绝缘膜）9A和元件隔离膜9B的步骤和用于注入和扩散硼的步骤 离子，并且在用于在氧化膜和多晶硅膜层叠在基板上的状态下通过选择性氧化形成选择性氧化物膜9A和元件隔离膜9B的步骤中，仅漂移区形成区域为 在去除多晶硅膜的状态下选择性氧化。

公开(公告)号：US06255154B1

公开(公告)日：2001-07-03

申请号：US09512520

申请日：2000-02-24

申请人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

发明人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

IPC分类号： H01L218238

CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L29/1095 ,  H01L29/7835

摘要： A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.

摘要翻译： 半导体器件包括源极区域4，沟道区域8，漏极区域5和栅极电极，其被图案化，使得其侧壁成锥形以朝向顶部更窄。 在沟道区域8和漏极区域5之间形成漂移区域22，以便在栅极电极7A（第一N-层22A）的下方并且在漏极区域5（第二N-层22B）附近的深处。 该配置有助于提高耐压并降低半导体器件的“导通”电阻。

公开(公告)号：US06713331B2

公开(公告)日：2004-03-30

申请号：US09944452

申请日：2001-08-31

申请人： Eiji Nishibe ,  Shuichi Kikuchi ,  Takuya Suzuki

发明人： Eiji Nishibe ,  Shuichi Kikuchi ,  Takuya Suzuki

IPC分类号： H01L21336

CPC分类号： H01L29/66659 ,  H01L29/42368 ,  H01L29/7835

摘要： A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.

摘要翻译： 半导体器件设置有在其上设置有栅氧化膜的基板上形成的栅电极。 在栅极旁边形成低浓度和高浓度的源极 - 漏极区域。 源极 - 漏极区的源极侧的扩散区宽度至少小于漏极侧的扩散区宽度。

公开(公告)号：US06696734B2

公开(公告)日：2004-02-24

申请号：US09829258

申请日：2001-04-09

申请人： Shuichi Kikuchi ,  Eiji Nishibe ,  Takuya Suzuki

发明人： Shuichi Kikuchi ,  Eiji Nishibe ,  Takuya Suzuki

IPC分类号： H01L2976

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L29/7835

摘要： A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N− type drain region formed so as to be adjacent to the gate electrode, a high concentration N+ type drain region separated from the other end of said gate electrode and included in said low N− type drain region, and a middle concentration N type layer having high impurity concentration peak at a position of the predetermined depth in said substrate at a region spanning at least from said gate electrode to said high concentration N+ type drain region, and formed so that high impurity concentration becomes low at a region near surface of the substrate.

摘要翻译： 半导体器件具有通过栅极绝缘膜形成在P型半导体衬底上的栅极电极，与栅电极相邻形成的低浓度N-型漏极区域，与另一端分离的高浓度N +型漏极区域 并且包括在所述低N型漏极区中的中等浓度N型层和在所述衬底中至少从所述栅电极到所述高电压的区域在所述衬底中的预定深度的位置处具有高杂质浓度的中等浓度N型层 浓度N +型漏极区域，并且形成为使得在衬底的表面附近的区域中高杂质浓度变低。

公开(公告)号：US06740932B2

公开(公告)日：2004-05-25

申请号：US09837397

申请日：2001-04-18

申请人： Shuichi Kikuchi ,  Eiji Nishibe ,  Takuya Suzuki

发明人： Shuichi Kikuchi ,  Eiji Nishibe ,  Takuya Suzuki

IPC分类号： H01L2976

CPC分类号： H01L29/66659 ,  H01L29/0847 ,  H01L29/7835

摘要： A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N− type drain region formed so as to be adjacent to the gate electrode, a high concentration N+ type drain region separated from the other end of said gate electrode and included in said low N− type drain region, and a middle concentration N type layer at a region spanning at least from said gate electrode to said high concentration N+ type drain region, and formed so that impurity concentration becomes low at a region near the gate electrode.

摘要翻译： 半导体器件具有通过栅极绝缘膜形成在P型半导体衬底上的栅极电极，与栅电极相邻形成的低浓度N-型漏极区域，与另一端分离的高浓度N +型漏极区域 并且包括在所述低N型漏极区中的中等浓度N型层和至少从所述栅电极到所述高浓度N +型漏极区的区域的中等浓度N型层，并且形成为使得杂质浓度变低 栅电极附近的区域。

公开(公告)号：US07161210B2

公开(公告)日：2007-01-09

申请号：US10738002

申请日：2003-12-17

申请人： Eiji Nishibe ,  Shuichi Kikuchi ,  Takuya Suzuki

发明人： Eiji Nishibe ,  Shuichi Kikuchi ,  Takuya Suzuki

IPC分类号： H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66659 ,  H01L29/42368 ,  H01L29/7835

摘要： A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.

摘要翻译： 半导体器件设置有在其上设置有栅氧化膜的基板上形成的栅电极。 在栅极旁边形成低浓度和高浓度的源极 - 漏极区域。 源极 - 漏极区的源极侧的扩散区宽度至少小于漏极侧的扩散区宽度。

公开(公告)号：US07056797B2

公开(公告)日：2006-06-06

申请号：US09829876

申请日：2001-04-10

申请人： Shuichi Kikuchi ,  Eiji Nishibe ,  Takuya Suzuki

发明人： Shuichi Kikuchi ,  Eiji Nishibe ,  Takuya Suzuki

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L29/7835

摘要： A semiconductor device has a gate electrode formed extending on a first and second gate insulation films formed on P type semiconductor substrate, an N+ type source region adjacent to one end of the gate electrode, an N− type drain region facing said source region through a channel region, having high impurity concentration peak at a position of the predetermined depth at least in said substrate under said first gate insulation film, and formed so that high impurity concentration becomes low at a region near surface of the substrate, an N− type drain region formed so as to range to the N− type drain region, an N+ type drain region separated from the other end of said gate electrode and included in said N− type drain region, and an N type layer formed so as to span from one end portion of said first gate insulation film to said N+ type drain region.

摘要翻译： 半导体器件具有形成在形成在P型半导体衬底上的第一和第二栅极绝缘膜上延伸的栅极电极，与栅极电极的一端相邻的N +型源极区域，通过 在所述第一栅极绝缘膜的至少所述基板的至少在所述基板的规定深度的位置处具有高的杂质浓度峰值，并且形成为使得在所述基板的表面附近的区域的高杂质浓度变低， 形成为与N型漏极区域相对应的区域，与所述栅极电极的另一端分离并包含在所述N型漏极区域中的N +型漏极区域，以及形成为从一个 所述第一栅极绝缘膜的端部到所述N +型漏极区。

公开(公告)号：US09693492B2

公开(公告)日：2017-06-27

申请号：US14111107

申请日：2012-01-31

申请人： Yusuke Kitsukawa ,  Takuya Suzuki ,  Tomoyuki Unno

发明人： Yusuke Kitsukawa ,  Takuya Suzuki ,  Tomoyuki Unno

IPC分类号： H05K1/11 ,  H05K1/14 ,  H05K9/00 ,  H01L23/04 ,  H01L23/552 ,  H01L23/66

CPC分类号： H05K9/006 ,  H01L23/04 ,  H01L23/552 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/3025

摘要： A high-frequency package includes a first dielectric substrate having a signal line and a grounding conductor provided on a back side, a high-frequency element connected to a back side of the first dielectric substrate with a first connection conductor therebetween, a second dielectric substrate having a signal line and a grounding conductor provided on a front side facing the back side with the high-frequency element therebetween, and second connection conductors that are arranged so as to surround the high-frequency element and connect the grounding conductor on the back side of the first dielectric substrate and the grounding conductor on the front side of the second dielectric substrate. In the high-frequency package, a dielectric space surrounded by a conductor pattern is formed in the front side of the second dielectric substrate under the high-frequency element.

公开(公告)号：US09433080B2

公开(公告)日：2016-08-30

申请号：US13075779

申请日：2011-03-30

申请人： Takuya Suzuki

发明人： Takuya Suzuki

IPC分类号： H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H01L23/552 ,  H01L23/58 ,  H01L23/66 ,  H01L25/18 ,  H01P5/107 ,  H01L25/065 ,  H01P3/08 ,  H01Q9/04 ,  H01L23/498 ,  H01L23/50 ,  H05K3/34

CPC分类号： H05K1/0218 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/552 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/18 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2225/0652 ,  H01L2924/15321 ,  H01L2924/1903 ,  H01L2924/19032 ,  H01L2924/3011 ,  H01P3/081 ,  H01P5/107 ,  H01Q9/04 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/0243 ,  H05K3/3436 ,  H05K2201/09618 ,  H05K2201/10151 ,  H05K2201/10734

摘要： Shielding of high-frequency circuits is achieved using a simple and inexpensive configuration not using any lid. A high-frequency circuit mounting substrate (20) is disposed, on an underside surface layer of which are disposed high-frequency circuits (21 and 22) and is formed a first grounding conductor that has same electric potential as grounding conductors of the high-frequency circuits and that surrounds the high-frequency circuits. A mother control substrate (3) is disposed, on which the high-frequency circuit mounting substrate (20) is mounted in such a way that the high-frequency circuits are sandwiched therebetween and on which a second grounding conductor is formed in a region facing the high-frequency circuits. Plural first lands are formed on the first grounding conductor of the high-frequency circuit mounting substrate (20) to surround the high-frequency circuits. Plural second lands are formed that are electrically connected to the second grounding conductor at positions on a surface layer of the mother control substrate (3) which face the first lands. Plural solder balls (30G2) are disposed for connecting the first lands and the second lands. The high-frequency circuits are housed in pseudo shielding cavities surrounded by the solder balls (30G2), the grounding conductors of the high-frequency circuits, and the first and second grounding conductors.