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    Method of manufacturing semiconductor device with capacitor and transistor
    1.
    发明授权
    Method of manufacturing semiconductor device with capacitor and transistor 有权
    制造具有电容器和晶体管的半导体器件的方法

    公开(公告)号：US07419874B2

    公开(公告)日：2008-09-02

    申请号：US11330402

    申请日：2006-01-12

    申请人： Tatsuya Fujishima ,  Mikio Fukuda ,  Yuji Tsukada ,  Keiji Ogata ,  Izuo Iida

    发明人： Tatsuya Fujishima ,  Mikio Fukuda ,  Yuji Tsukada ,  Keiji Ogata ,  Izuo Iida

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/0629 ,  H01L21/823462 ,  H01L28/40

    摘要： The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.

    摘要翻译： 本发明是为了防止具有形成在同一半导体衬底上的电容器和MOS晶体管的半导体器件中的电容器的电介质击穿。 在P型半导体衬底的整个表面上形成作为高电压MOS晶体管的栅极绝缘膜的SiO 2膜。 在高电压MOS晶体管形成区域和覆盖与电容器形成区域相邻的沟槽隔离膜的边缘的SiO 2膜的一部分上选择性地形成光致抗蚀剂层，并且SiO 2 使用该光致抗蚀剂层作为掩模通过蚀刻除去膜。 由于在该蚀刻中光致抗蚀剂层用作掩模，所以与电容器相邻的沟槽隔离膜的边缘不被切割得太深。 在该蚀刻中残留的SiO 2膜和之后形成的SiO 2膜形成电容器绝缘膜。

    Semiconductor device manufacturing method
    2.
    发明申请
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号：US20060172488A1

    公开(公告)日：2006-08-03

    申请号：US11330402

    申请日：2006-01-12

    申请人： Tatsuya Fujishima ,  Mikio Fukuda ,  Yuji Tsukada ,  Keiji Ogata ,  Izuo Iida

    发明人： Tatsuya Fujishima ,  Mikio Fukuda ,  Yuji Tsukada ,  Keiji Ogata ,  Izuo Iida

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/0629 ,  H01L21/823462 ,  H01L28/40

    摘要： The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.

    摘要翻译： 本发明是为了防止具有形成在同一半导体衬底上的电容器和MOS晶体管的半导体器件中的电容器的电介质击穿。 在P型半导体衬底的整个表面上形成作为高电压MOS晶体管的栅极绝缘膜的SiO 2膜。 在高电压MOS晶体管形成区域和覆盖与电容器形成区域相邻的沟槽隔离膜的边缘的SiO 2膜的一部分上选择性地形成光致抗蚀剂层，并且SiO 2 使用该光致抗蚀剂层作为掩模通过蚀刻除去膜。 由于在该蚀刻中光致抗蚀剂层用作掩模，所以与电容器相邻的沟槽隔离膜的边缘不被切割得太深。 在该蚀刻中残留的SiO 2膜和之后形成的SiO 2膜形成电容器绝缘膜。

    Semiconductor device and method of manufacturing the same
    3.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体器件及其制造方法

    公开(公告)号：US06614075B2

    公开(公告)日：2003-09-02

    申请号：US09852540

    申请日：2001-05-10

    申请人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

    发明人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

    IPC分类号： H01L2978

    CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L29/1095 ,  H01L29/7835

    摘要： A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.

    摘要翻译： 半导体器件包括源极区域4，沟道区域8，漏极区域5和栅极电极，其被图案化，使得其侧壁是锥形的，以朝向顶部更窄。 在沟道区域8和漏极区域5之间形成漂移区域22，以便在栅极电极7A（第一N-层22A）的下方并且在漏极区域5（第二N-层22B）附近的深处。 该配置有助于提高耐压并降低半导体器件的“导通”电阻。

    Manufacturing method of semiconductor integrated circuit device
    5.
    发明申请
    Manufacturing method of semiconductor integrated circuit device 审中-公开
    半导体集成电路器件的制造方法

    公开(公告)号：US20060008962A1

    公开(公告)日：2006-01-12

    申请号：US11175049

    申请日：2005-07-06

    申请人： Kazuyuki Ozeki ,  Yuji Tsukada

    发明人： Kazuyuki Ozeki ,  Yuji Tsukada

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823481 ,  H01L21/823462

    摘要： The invention is directed to a semiconductor integrated circuit device having a plurality of gate insulation films of different thicknesses where reliability of the gate insulation films and characteristics of MOS transistors are improved. A photoresist layer is selectively formed on a SiO2 film in first and third regions, and a SiO2 film in a second region is removed by etching. After the photoresist layer is removed, a silicon substrate is thermally oxidized to form a SiO2 film having a smaller thickness than a first gate insulation film in the second region. Then, the SiO2 film in the third region is removed by etching. After a photoresist layer is removed, the silicon substrate is thermally oxidized to form a SiO2 film having a smaller thickness than a second gate insulation film in the third region.

    摘要翻译： 本发明涉及一种半导体集成电路器件，其具有多个不同厚度的栅极绝缘膜，其中栅极绝缘膜的可靠性和MOS晶体管的特性得到改善。 在第一和第三区域中的SiO 2膜上选择性地形成光致抗蚀剂层，并且通过蚀刻去除第二区域中的SiO 2膜。 在除去光致抗蚀剂层之后，硅衬底被热氧化以形成在第二区域中具有比第一栅极绝缘膜更薄的厚度的SiO 2膜。 然后，通过蚀刻除去第三区域中的SiO 2膜。 在去除光致抗蚀剂层之后，硅衬底被热氧化以形成具有比第三区域中的第二栅极绝缘膜更薄的厚度的SiO 2膜。

    Semiconductor device manufacturing method
    6.
    发明申请
    Semiconductor device manufacturing method 审中-公开
    半导体器件制造方法

    公开(公告)号：US20050224794A1

    公开(公告)日：2005-10-13

    申请号：US11087742

    申请日：2005-03-24

    申请人： Naoaki Tanaka ,  Yuji Tsukada ,  Yuichi Watanabe

    发明人： Naoaki Tanaka ,  Yuji Tsukada ,  Yuichi Watanabe

    IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/78 ,  H01L29/04

    CPC分类号： H01L21/32137 ,  H01L21/02087 ,  H01L21/32115 ,  H01L21/7684

    摘要： The invention provides a method of forming an electrode or wiring which prevents reattachment of an etching residue in following processes by removing the etching residue at a bevel portion of a semiconductor wafer. An insulation film is formed so as to cover a front surface and a back surface of a semiconductor wafer, and then a conductive film is formed on a whole surface of the insulation film. Next, a photoresist layer is selectively formed on the conductive film by an exposure and development process. The conductive film is then selectively removed by an isotropic etching with using this photoresist layer as a mask, thereby forming an electrode or wiring of a semiconductor device. Since the electrode or the wiring of the semiconductor device is formed by isotropically etching the conductive film, a hangnail-like etching residue causing dust does not occur at the bevel portion of the wafer even though the conductive film remains on the back side of the semiconductor wafer.

    摘要翻译： 本发明提供一种形成电极或布线的方法，其通过去除半导体晶片的斜面部分处的蚀刻残留物来防止在后面的过程中重新附着蚀刻残留物。 形成绝缘膜以覆盖半导体晶片的前表面和后表面，然后在绝缘膜的整个表面上形成导电膜。 接下来，通过曝光和显影处理在导电膜上选择性地形成光致抗蚀剂层。 然后通过使用该光致抗蚀剂层作为掩模的各向同性蚀刻选择性地去除导电膜，从而形成半导体器件的电极或布线。 由于半导体器件的电极或布线通过各向同性地蚀刻导电膜而形成，因此即使导电膜保留在半导体的背面，也不会在晶片的斜面部分处产生引起灰尘的吊坠状蚀刻残留物 晶圆。

    Semiconductor device and method of manufacturing the same
    8.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06255154B1

    公开(公告)日：2001-07-03

    申请号：US09512520

    申请日：2000-02-24

    申请人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

    发明人： Yumiko Akaishi ,  Takuya Suzuki ,  Shinya Mori ,  Yuji Tsukada ,  Yuichi Watanabe ,  Shuichi Kikuchi

    IPC分类号： H01L218238

    CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L29/1095 ,  H01L29/7835

    摘要： A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.

    摘要翻译： 半导体器件包括源极区域4，沟道区域8，漏极区域5和栅极电极，其被图案化，使得其侧壁成锥形以朝向顶部更窄。 在沟道区域8和漏极区域5之间形成漂移区域22，以便在栅极电极7A（第一N-层22A）的下方并且在漏极区域5（第二N-层22B）附近的深处。 该配置有助于提高耐压并降低半导体器件的“导通”电阻。