公开(公告)号：US06880150B1

公开(公告)日：2005-04-12

申请号：US09301284

申请日：1999-04-28

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/44

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当指令解码器409a〜409c解码分支指令时，分支指令中包含的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US07076638B2

公开(公告)日：2006-07-11

申请号：US10246482

申请日：2002-09-19

申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

IPC分类号： G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

公开(公告)号：US07073169B2

公开(公告)日：2006-07-04

申请号：US10174108

申请日：2002-06-17

申请人： Hajime Ogawa ,  Shuichi Takayama ,  Taketo Heishi ,  Nobuo Higaki

发明人： Hajime Ogawa ,  Shuichi Takayama ,  Taketo Heishi ,  Nobuo Higaki

IPC分类号： G06F9/45

CPC分类号： G06F8/4441

摘要： A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a conditional executable instruction that is executed when a condition that the conditional executable instruction refers to is satisfied. In the case where there is a section containing a non-executive condition under which no instruction is executed in one cycle or a plurality of cycles in series, the branch instruction insertion unit inserts a conditional branch instruction that refers to the non-executive condition and instructs to branch to a cycle immediately after a last cycle of the section, to after an instruction of a cycle immediately before a start of the section. Thus, a compiler device employing conditional executable instructions is provided that is capable of generating an assembler code that does not degrade the performance when the instructions are executed, even if a source program includes a branch instruction that causes a then part and an else part to be executed through unbalanced numbers of cycles, respectively.

摘要翻译： 编译器装置包括条件可执行指令生成单元和分支指令插入单元。 条件可执行指令生成单元生成当满足条件可执行指令引用的条件时执行的条件可执行指令。 在存在包含在一个周期或多个周期中不执行指令的非执行条件的部分的情况下，分支指令插入单元插入参考非执行条件的条件分支指令，并且 指示在该部分的最后一个周期之后立即分支到一个周期，直到在该部分开始之前的一个周期的指令之后。 因此，提供了一种使用条件可执行指令的编译器装置，其能够生成当执行指令时不降低性能的汇编代码，即使源程序包括分支指令，该分支指令导致随后的部分和其他部分 分别通过不平衡的周期数执行。

公开(公告)号：US20060031661A1

公开(公告)日：2006-02-09

申请号：US11245357

申请日：2005-10-07

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/40

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US06904135B2

公开(公告)日：2005-06-07

申请号：US10172216

申请日：2002-06-14

申请人： Shuichi Takayama ,  Nobuo Higaki ,  Hajime Ogawa ,  Taketo Heishi

发明人： Shuichi Takayama ,  Nobuo Higaki ,  Hajime Ogawa ,  Taketo Heishi

IPC分类号： H04B1/38 ,  H04B7/26 ,  H04M1/00 ,  H04M1/723 ,  H04M1/725 ,  H04N5/44 ,  H04W4/24 ,  H04W76/02 ,  H04W88/02 ,  H04W88/08 ,  H04W88/14 ,  H04M11/00 ,  H04B1/00

CPC分类号： H04B1/005 ,  H04B1/3805 ,  H04M1/725 ,  H04N5/4401 ,  H04N21/2408 ,  H04N21/2543 ,  H04N21/4126 ,  H04N21/4263 ,  H04N21/42676 ,  H04N21/433 ,  H04N21/43637 ,  H04N21/44227 ,  H04N21/443 ,  H04N21/6112 ,  H04N21/6162 ,  H04N21/6168 ,  H04N21/654 ,  H04N21/6582 ,  H04N21/6583

摘要： A compound device has the structural hardware of a digital television, is connected to an antenna and a telephone station, and by reading out and running either a digital television (DTV) program or a base station program with a general processor, it has both the function of a digital television and the function of a portable telephone base station. The owner of the compound device receives discounts in their subscribed telephone fee or their power fee based on records in a communication record portion. Thus, a compound device in which a digital television is given the function of a portable telephone base station is provided, so that a novel infrastructure can be achieved in which insufficiencies in base stations are made up for without requiring equipment investment expenditures and portable device owners are given financial benefits in compensation for allowing the public use of their private possession as a portable telephone base station.

摘要翻译： 复合设备具有数字电视的结构硬件，连接到天线和电话台，并且通过读取和运行数字电视（DTV）程序或使用通用处理器的基站程序，它具有 数字电视的功能和便携式电话基站的功能。 复合设备的所有者根据通信记录部分中的记录，收到其订阅的电话费或其电费的折扣。 因此，提供了数字电视机被赋予便携式电话基站的功能的复合装置，从而可以实现基站的不足之处，不需要设备投资支出和便携式设备所有者的新颖的基础设施 给予经济利益，允许公共使用私人拥有作为便携式电话基站。

公开(公告)号：US07761692B2

公开(公告)日：2010-07-20

申请号：US11452282

申请日：2006-06-14

申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

IPC分类号： G06F9/38 ,  G06F9/45

CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

摘要翻译： 为了克服有条件执行的指令如果不满足条件而被执行为无操作指令的问题，导致硬件的利用效率差并且降低了有效性能，则处理器解码大于 提供的计算单元的数量并且在执行阶段之前用指令发布控制部分判断其执行条件，条件为假的指令被无效，并且分配后续的有效指令，使得有效地使用计算单元（硬件）。 编译器执行调度，使得执行条件为真的指令数量不超过硬件的并行度的上限。 在每个周期上平行布置的指令数可能超过硬件的并行程度。

公开(公告)号：US20060242387A1

公开(公告)日：2006-10-26

申请号：US11452282

申请日：2006-06-14

申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

IPC分类号： G06F9/44

CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

公开(公告)号：US06976245B2

公开(公告)日：2005-12-13

申请号：US10012725

申请日：2001-10-22

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G09F9/44

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US07080367B2

公开(公告)日：2006-07-18

申请号：US10051335

申请日：2001-10-19

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/45

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US06976250B2

公开(公告)日：2005-12-13

申请号：US10045802

申请日：2001-10-19

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F717/151

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。