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    Method of fabricating semiconductor structures for latch-up suppression
    1.
    发明授权
    Method of fabricating semiconductor structures for latch-up suppression 失效
    制造用于闭锁抑制的半导体结构的方法

    公开(公告)号：US07648869B2

    公开(公告)日：2010-01-19

    申请号：US11330689

    申请日：2006-01-12

    申请人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/0921 ,  H01L21/823878

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁相邻的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。

    Well isolation trenches (WIT) for CMOS devices
    4.
    发明授权
    Well isolation trenches (WIT) for CMOS devices 失效
    用于CMOS器件的隔离沟槽（WIT）

    公开(公告)号：US07737504B2

    公开(公告)日：2010-06-15

    申请号：US11759981

    申请日：2007-06-08

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L29/772

    CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

    摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

    摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

    Methods and semiconductor structures for latch-up suppression using a conductive region
    9.
    发明授权
    Methods and semiconductor structures for latch-up suppression using a conductive region 失效
    使用导电区域进行闩锁抑制的方法和半导体结构

    公开(公告)号：US07727848B2

    公开(公告)日：2010-06-01

    申请号：US12169806

    申请日：2008-07-09

    申请人： Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L21/331

    CPC分类号： H01L27/0921 ,  H01L21/823878 ,  H01L29/78

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 半导体结构包括形成在衬底的半导体材料中的第一和第二相邻的掺杂阱。 在第一和第二掺杂阱之间的衬底中限定了包括基底和基底与顶表面之间的第一侧壁的沟槽。 沟槽部分地填充有与第一和第二掺杂阱电耦合的导体材料。 可以在与沟槽中的导电材料相邻的位置处与沟槽邻接的半导体材料中提供高度掺杂的导电区域。