摘要:
Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
摘要:
Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要:
This invention relates to an improved method for conducting peritoneal dialysis with a decreased total volume of dialysis fluid used and increased efficacy parameters such as ultrafiltration rate, urea clearance rate and dialysate volume as compared to conventional techniques. In the method of this invention, a fluid communication through the peritoneal membrane into the peritoneal cavity of a patient in need of peritoneal dialysis treatment is established. An initial volume of an aqueous peritoneal dialysis composition containing an osmotic agent is instilled into the peritoneal cavity through the fluid communication. The dialysis composition contains an amount of dissolved osmotic agent (i) that is insufficient to adequately dialyze the patient during a predetermined time period of dialysis treatment, but (ii) that is present at an osmolarity that is greater than the osmolarity of the body fluids in contact with the membrane, such that an osmolarity gradient is created across the membrane between the composition and the body fluids. A flux of water and solute enters the composition from the body fluids by means of that gradient.A further amount of dissolved osmotic agent is released into the instilled dialysis composition to form a modified dialysis composition. That further osmotic agent is released in an amount sufficient to maintain a substantially constant osmolarity gradient between the modified dialysis composition and the body fluids such that the water and solute flux continues to enter into the modified dialysis composition during the predetermined dialysis time period. The modified dialysis composition is substantially removed from the peritoneal cavity at the end of the treatment time period.
摘要:
Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.
摘要:
A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要:
A monitor semiconductor chip that incorporates ESD sensitive resistors is subjected to the same steps in a semiconductor manufacturing process to which functional semiconductor chips are subjected. The ESD sensitive resistors are configured to experience non-volatile changes in resistance in response to ESD events, such that the resistors retain the changes in resistance after dissipation of the ESD events have occurred. As a result, the occurrence of an ESD event, and in some instances, the magnitude of an ESD event, can be detected by monitoring the resistance of the ESD sensitive resistors after one or more steps in a semiconductor manufacturing process.
摘要:
An ESD protection circuit which may be implemented in thin epitaxial substrate surfaces. The protection device includes a MOSFET transistor or bipolar transistor implemented in a trench isolated area of the substrate. The isolation of the MOSFET transistor permits the substrate region to be pumped with an electric charge which reduces the trigger/snapback voltage and MOSFET threshold voltage for the device. A trigger current supplies the pumping current to the isolated substrate area when a transient voltage is applied thus lowering the trigger/snapback voltage of the MOSFET transistor in the presence of a transient voltage.
摘要:
A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.
摘要:
An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.
摘要:
A structure for increasing the threshold voltage of a corner device, particularly for shallow trench isolation having narrow devices. An FET comprises a substrate having a channel formed therein under a gate between spaced source and drain regions. A trench isolation region is formed in the substrate around the transistor and on opposite sides of the channel to isolate the transistor from other devices formed in the substrate, with the trench isolation region forming first and second junction corner devices with opposite sides of the channel. A first dielectric layer is formed under the gate and over the channel of the field effect transistor to form a gate insulator for the transistor. A second corner edge dielectric layer is formed under the gate structure and over the first and second corner devices, such that the corner edge dielectric layer increases the thickness of dielectric over each corner device and thus increases the threshold voltage (Vt) and edge dielectric breakdown and decreases MOSFET corner gate-induced drain leakage.