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    Wireless communications system, base station, and mobile station
    1.
    发明授权
    Wireless communications system, base station, and mobile station 有权
    无线通信系统，基站和移动台

    公开(公告)号：US08885618B2

    公开(公告)日：2014-11-11

    申请号：US12959808

    申请日：2010-12-03

    Applicant: Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    Inventor： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    IPC: H04B7/212 ,  H04N5/225 ,  H04W72/00 ,  H04W36/38 ,  H04W36/00 ,  H04W72/04 ,  H04B7/26 ,  H04W4/02 ,  H04W56/00

    CPC classification number: H04W36/38 ,  H04B7/2643 ,  H04B7/2656 ,  H04W4/02 ,  H04W36/0088 ,  H04W56/00 ,  H04W72/04 ,  H04W72/0446

    Abstract: A wireless communications system including a mobile station MS and base stations BS1 and BS2, wherein one or both of the mobile station MS and the base stations BS1 and BS2 is provided with a unit for notifying information of a frame position with the possibility of transmission of packets based on detection of deterioration of a reception quality and wherein the mobile station MS is provided with a unit for determining a frame position without the possibility of transmission of packets and shifting to a peripheral cell detection mode at this frame position based on information of a frame position with the possibility of transmission of packets, whereby it is possible to shift to a peripheral cell detection mode without lowering the transmission efficiency and without complicating the processing.

    Abstract translation: 一种包括移动站MS和基站BS1和BS2的无线通信系统，其中，移动站MS和基站BS1和BS2之一或两者设置有用于通知具有帧位置信息的单元， 基于检测到接收质量恶化的分组，并且其中移动台MS设置有用于确定帧位置的单元，而不具有传输分组的可能性并且基于信息的信息移动到该帧位置处的周边小区检测模式 具有发送分组的可能性的帧位置，由此可以在不降低传输效率的情况下移动到周边小区检测模式，并且不会使处理复杂化。

    Transmission device, encoding device and decoding device
    2.
    发明授权
    Transmission device, encoding device and decoding device 有权
    传输设备，编码设备和解码设备

    公开(公告)号：US08028223B2

    公开(公告)日：2011-09-27

    申请号：US12068707

    申请日：2008-02-11

    Applicant: Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano ,  Takashi Dateki ,  Mitsuo Kobayashi ,  Junya Mikami

    Inventor： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano ,  Takashi Dateki ,  Mitsuo Kobayashi ,  Junya Mikami

    IPC: G06F11/00 ,  H03M13/00

    CPC classification number: H03M13/2957 ,  H03M13/6306 ,  H03M13/635 ,  H03M13/6356 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/1812

    Abstract: Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are not inserted, a dummy bit insertion portion inserts dummy bits into the information bits and shifts the decoding characteristic, so that the code rate assumes a value outside a specific range determined by the decoding characteristic after shifting. An encoding portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the encoding to generate a systematic code, and a rate matching portion, performs rate matching such that the size of the systematic code is equal to a size determined by the physical channel transmission rate, and transmits the systematic code.

    Abstract translation: 公开了一种发送装置，其发送通过将奇偶校验位加到信息比特而获得的系统代码。 当在未插入虚拟位的情况下，系统代码的码率是由解码特性确定的特定范围内的值时，伪位插入部分将伪位插入信息位并移位解码特性，使得 码率假定在移位之后由解码特性确定的特定范围之外的值。 编码部分对虚拟位被插入的信息比特进行系统编码，并且从编码结果中删除伪比特以产生系统代码，并且速率匹配部分执行速率匹配， 系统码等于由物理信道传输速率确定的大小，并传输系统码。

    Transmitting apparatus with bit arrangement method
    3.
    发明授权
    Transmitting apparatus with bit arrangement method 有权
    带排列方式的发送装置

    公开(公告)号：US07860186B2

    公开(公告)日：2010-12-28

    申请号：US10899068

    申请日：2004-07-27

    Applicant: Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    Inventor： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    IPC: H04L27/36

    CPC classification number: H04L27/3488 ,  H03M13/25 ,  H03M13/2957 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0067 ,  H04L1/16

    Abstract: A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block to be closer to an occupation rate occupied with predetermined bits included in the second data block in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.

    Abstract translation: 一种发送装置，包括可操作以使用包括在第一数据块和第二数据块中的比特来生成多个比特序列的电路，所述电路可操作以控制所述多个比特序列以对应于所述相位平面上的信号点，包括比特 序列产生单元，其可操作以控制比特序列的生成，以调整占据第一数据块中包含的预定比特占有率的占有率，以使其相对于第二数据块中包含的预定比特占据的占用率更接近第 基于由与相位平面上的信号点的对应产生的相应比特序列的误差容限，以及可操作以根据每个信号点发送通过多电平调制获得的信号的电路。

    Data receiving apparatus and hybrid-ARQ communication system
    4.
    发明授权
    Data receiving apparatus and hybrid-ARQ communication system 有权
    数据接收装置和混合ARQ通信系统

    公开(公告)号：US07500166B2

    公开(公告)日：2009-03-03

    申请号：US11152902

    申请日：2005-06-15

    Applicant: Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano

    Inventor： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Tetsuya Yano

    IPC: G08C25/02 ,  H04L1/18

    CPC classification number: H04L1/1812 ,  H04L1/1819 ,  H04L1/1845 ,  H04L1/201

    Abstract: A receiver receives data transmitted from a transmitter. The data is stored in a buffer, and a reliability value of the data is computed by a computing unit. A determining unit determines reliability of the data by comparing a reliability value of existing data in the buffer and a reliability value of the data. When the reliability value of the data is higher than a predetermined value, the existing data is combined with the data. Then, an error correcting unit performs error correcting on combined data obtained, and outputs decoded bits. If the combined data includes many errors, retransmission of the data is requested to the transmitter. When the reliability value of the data is lower than the predetermined value, retransmission of data is directly requested without combining the data with the existing data.

    Abstract translation: 接收机接收从发射机发送的数据。 数据存储在缓冲器中，数据的可靠性值由计算单元计算。 确定单元通过比较缓冲器中现有数据的可靠性值和数据的可靠性值来确定数据的可靠性。 当数据的可靠性值高于预定值时，将现有数据与数据组合。 然后，错误校正单元对获得的组合数据执行纠错，并输出解码的比特。 如果组合数据包含许多错误，则向发射机请求数据的重传。 当数据的可靠性值低于预定值时，直接请求重发数据而不将数据与现有数据进行组合。

    Transmitting apparatus with bit arrangement method
    5.
    发明申请
    Transmitting apparatus with bit arrangement method 有权
    带排列方式的发送装置

    公开(公告)号：US20050180363A1

    公开(公告)日：2005-08-18

    申请号：US10899068

    申请日：2004-07-27

    Applicant: Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    Inventor： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    IPC: H03M13/25 ,  H03M13/29 ,  H04B7/216 ,  H04J13/00 ,  H04L1/00 ,  H04L1/16 ,  H04L12/66 ,  H04L27/00 ,  H04L27/34

    CPC classification number: H04L27/3488 ,  H03M13/25 ,  H03M13/2957 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0067 ,  H04L1/16

    Abstract: A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block to be closer to an occupation rate occupied with predetermined bits included in the second data block in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.

    Abstract translation: 一种发送装置，包括可操作以使用包括在第一数据块和第二数据块中的比特来生成多个比特序列的电路，所述电路可操作以控制所述多个比特序列以对应于所述相位平面上的信号点，所述电路包括位 序列产生单元，其可操作以控制比特序列的生成，以调整占据第一数据块中包含的预定比特占有率的占有率，以使其相对于第二数据块中包含的预定比特占据的占用率更接近第 基于由与相位平面上的信号点的对应产生的相应比特序列的误差容限，以及可操作以根据每个信号点发送通过多电平调制获得的信号的电路。

    Transmitting apparatus with bit arrangement method
    9.
    发明授权
    Transmitting apparatus with bit arrangement method 有权
    带排列方式的发送装置

    公开(公告)号：US08085872B2

    公开(公告)日：2011-12-27

    申请号：US13032255

    申请日：2011-02-22

    Applicant: Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    Inventor： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    IPC: H03C1/52

    CPC classification number: H04L27/3488 ,  H03M13/25 ,  H03M13/2957 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0067 ,  H04L1/16

    Abstract: A method of transmitting data that includes controlling generation of bit sequences to adjust an occupation rate occupied with predetermined bits included in a first data block, which is obtained by encoding first data in a first encoding process, to be equal or closer to an occupation rate occupied with predetermined bits included in a second data block, which is obtained by encoding second data in a second encoding process, in regard to first bit positions of the bit sequences generated using bits included in the first and second data blocks; and performing multi-level modulation for transmission based on the generated bit sequences.

    Abstract translation: 一种发送数据的方法，包括控制比特序列的生成，以将通过对第一编码处理中的第一数据进行编码而获得的第一数据块中包含的预定比特占有率的占有率调整为等于或接近占用率 关于使用包括在第一和第二数据块中的位产生的比特序列的第一比特位置，在第二编码处理中对第二数据进行编码而获得的第二数据块中包含的预定比特占用; 以及基于所生成的位序列执行用于传输的多电平调制。

    Transmitting apparatus with bit arrangement method
    10.
    发明授权
    Transmitting apparatus with bit arrangement method 有权
    带排列方式的发送装置

    公开(公告)号：US07965791B2

    公开(公告)日：2011-06-21

    申请号：US12836860

    申请日：2010-07-15

    Applicant: Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    Inventor： Tetsuya Yano ,  Kazuhisa Obuchi ,  Shunji Miyazaki

    IPC: H04L27/36

    CPC classification number: H04L27/3488 ,  H03M13/25 ,  H03M13/2957 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0067 ,  H04L1/16

    Abstract: A method of transmitting data including controlling generation of bit sequences to adjust an occupation rate occupied with predetermined bits included in a first data block, which is obtained by encoding first data, to be closer to an occupation rate occupied with predetermined bits included in a second data block, which is obtained by encoding second data. With regard to first bit positions of the predetermined bits, the first bit positions being distinguished from second bit positions based on an error tolerance resulting from a correspondence to a signal point on a phase plane. Wherein a sum of a number of the predetermined bits included in the first data block and the predetermined bits included in the second data block is less than a total number of the first bit positions. Also including performing multi-level modulation for transmission based on the generated bit sequences.

    Abstract translation: 一种发送数据的方法，包括控制比特序列的生成，以调整由第一数据块中包含的预定比特占用的占有率，所述占用率是通过对第一数据进行编码而获得的，以更接近于包含在第二数据包中的预定比特占用的占用率 数据块，其通过对第二数据进行编码而获得。 关于预定比特的第一比特位置，基于由相对于相位平面上的信号点的对应性产生的误差容限，第一比特位置与第二比特位置不同。 其中包括在第一数据块中的预定比特数和包括在第二数据块中的预定比特之和的总和小于第一比特位置的总数。 还包括基于所生成的位序列执行用于传输的多电平调制。

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