公开(公告)号：US08227863B2

公开(公告)日：2012-07-24

申请号：US11723481

申请日：2007-03-20

申请人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

发明人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

IPC分类号： H01L29/76

CPC分类号： H01L27/1237 ,  G11C16/349 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/78696 ,  H01L29/7881

摘要： A semiconductor layer having a channel formation region provided between a pair of impurity regions spaced from each other is provided, and a first insulating layer a floating gate, a second insulating layer, and a control gate are provided above the semiconductor layer. The semiconductor material forming the floating gate preferably has a band gap smaller than that of the semiconductor layer. The band gap of a channel formation region in the semiconductor material forming the floating gate is preferably smaller than that of the semiconductor layer by 0.1 eV or more.

摘要翻译： 提供具有设置在彼此间隔开的一对杂质区之间的沟道形成区的半导体层，并且在半导体层上方设置有第一绝缘层，浮栅，第二绝缘层和控制栅。 形成浮栅的半导体材料优选具有比半导体层小的带隙。 形成浮栅的半导体材料中的沟道形成区的带隙优选比半导体层的带隙小0.1eV以上。

公开(公告)号：US08212302B2

公开(公告)日：2012-07-03

申请号：US11723484

申请日：2007-03-20

申请人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

发明人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

IPC分类号： H01L29/76

CPC分类号： H01L29/42324 ,  H01L29/513 ,  H01L29/7883 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over the semiconductor substrate. The floating gate includes at least two layers. It is preferable that a band gap of a first layer included in the floating gate, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material for forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by lowering the bottom energy level of a conduction band of the floating gate electrode than that of the channel formation region in the semiconductor substrate, a carrier injecting property and a charge holding property are improved.

摘要翻译： 一种非易失性半导体存储器件，其特征在于具有在一对杂质区域之间形成沟道形成区域的半导体衬底和第一绝缘层，浮置栅极，第二绝缘层， 以及半导体衬底上的控制栅极。 浮栅包括至少两层。 与第一绝缘层接触的浮栅中包含的第一层的带隙优选小于半导体衬底的带隙。 例如，优选用于形成浮置栅极的半导体材料的带隙比半导体衬底中的沟道形成区域的带隙小0.1eV以上。 这是因为通过降低浮置栅电极的导带的底部能级比半导体衬底中的沟道形成区的底部能级降低，因此提高了载流子注入性和电荷保持性。

公开(公告)号：US07786526B2

公开(公告)日：2010-08-31

申请号：US11730184

申请日：2007-03-29

申请人： Tamae Takano ,  Makoto Furuno ,  Yoshinobu Asami ,  Shunpei Yamazaki

发明人： Tamae Takano ,  Makoto Furuno ,  Yoshinobu Asami ,  Shunpei Yamazaki

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/12 ,  H01L29/513

摘要： It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced. The nonvolatile semiconductor memory device includes a semiconductor region with a channel formation region formed between a pair of impurity regions which are formed to be apart from each other; and a first insulating layer, a charge accumulation layer, a second insulating layer, and a control gate are formed in a location which is a top layer portion of the semiconductor region and which roughly overlaps with the channel formation region. The charge accumulation layer is insulative and is formed as a layer in which electric charge can be trapped.

摘要翻译： 本发明的目的是提供一种具有优异的写入特性和电荷保持特性的非易失性半导体存储器件。 此外，本发明的目的是提供一种可以减小写入电压的非易失性半导体存储器件。 非易失性半导体存储器件包括：半导体区域，其具有在形成为彼此分开的一对杂质区域之间形成的沟道形成区域; 并且在作为半导体区域的顶层部分并且与沟道形成区域大致重叠的位置处形成第一绝缘层，电荷累积层，第二绝缘层和控制栅极。 电荷蓄积层是绝缘的，并且形成为能够俘获电荷的层。

公开(公告)号：US08729620B2

公开(公告)日：2014-05-20

申请号：US11723483

申请日：2007-03-20

申请人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

发明人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1214 ,  H01L29/7881

摘要： It is an object to provide a nonvolatile semiconductor memory device having excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate, a second insulating layer, and a control gate are provided. The floating gate has at least a two-layer structure, and a first layer in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. Furthermore, by setting an energy level at the bottom of the conduction band of the floating gate lower than that of the channel forming region of the semiconductor layer, injectability of carriers and a charge-retention property can be improved.

摘要翻译： 本发明的目的是提供具有优异的书写特性和电荷保持性的非易失性半导体存储器件。 提供了包括形成为彼此分开的一对杂质区之间的沟道形成区域的半导体层。 在其上层部分中，设置有第一绝缘层，浮栅，第二绝缘层和控制栅。 浮栅具有至少两层结构，与第一绝缘层接触的第一层优选具有比半导体层小的带隙。 此外，通过将浮置栅极的导带的底部的能级设定为低于半导体层的沟道形成区的能级，能够提高载流子的注入性和电荷保持性。

公开(公告)号：US08022460B2

公开(公告)日：2011-09-20

申请号：US11725487

申请日：2007-03-20

申请人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

发明人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

IPC分类号： H01L29/76

CPC分类号： H01L29/42324 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7883

摘要： An object is to provide a nonvolatile semiconductor memory device which is superior in writing property and charge holding property. A semiconductor substrate in which a channel formation region is formed between a pair of impurity regions is provided, and a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided over the semiconductor substrate. The floating gate electrode includes at least two layers. It is preferable that a band gap of a first floating gate electrode, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. It is also preferable that a second floating gate electrode be formed of a metal material, an alloy material, or a metal compound material. This is because, by lowering the bottom energy level of a conduction band of the floating gate electrode than that of the channel formation region in the semiconductor substrate, a carrier injecting property and a charge holding property can be improved.

摘要翻译： 本发明的目的是提供一种写入性和电荷保持性优异的非易失性半导体存储器件。 提供了在一对杂质区域之间形成沟道形成区域的半导体衬底，并且在半导体衬底上设置有第一绝缘层，浮栅电极，第二绝缘层和控制栅电极。 浮栅电极包括至少两层。 优选与第一绝缘层接触的第一浮栅的带隙小于半导体基板的带隙。 另外，优选第二浮栅电极由金属材料，合金材料或金属复合材料形成。 这是因为，通过降低浮置栅极的导带的底部能量水平比半导体衬底中的沟道形成区域的底部能量水平降低，可以提高载流子注入性和电荷保持性。

公开(公告)号：US07842992B2

公开(公告)日：2010-11-30

申请号：US11723506

申请日：2007-03-20

申请人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

发明人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

IPC分类号： H01L29/788

CPC分类号： H01L27/1237 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1214 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885

摘要： It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided. The floating gate has at least a two-layer structure, and a first layer being in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. The stability of the first layer is improved by formation of a second layer of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.

摘要翻译： 本发明的目的是提供具有优异的书写特性和电荷保持性的非易失性半导体存储器件。 提供了包括形成为彼此分开的一对杂质区之间的沟道形成区域的半导体层。 在其上层部分中，设置有第一绝缘层，浮栅电极，第二绝缘层和控制栅电极。 浮栅具有至少两层结构，与第一绝缘层接触的第一层优选具有比半导体层的带隙小的带隙。 通过使用金属，合金或金属复合材料形成第二层浮栅电极来改善第一层的稳定性。 浮栅电极的这种结构可以改善载体在书写中的注入性和电荷保持性。

公开(公告)号：US07692232B2

公开(公告)日：2010-04-06

申请号：US11723482

申请日：2007-03-20

申请人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

发明人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

IPC分类号： H01L29/76

CPC分类号： H01L27/105 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A nonvolatile semiconductor memory device which is superior in writing and charge holding properties, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over an upper layer portion of the semiconductor substrate. It is preferable that a band gap of a semiconductor material forming the floating gate be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by decreasing the bottom energy level of a conduction band of the floating gate electrode to be lower than that of the channel formation region in the semiconductor substrate, carrier injecting and charge holding properties are improved.

摘要翻译： 一种写入和电荷保持特性优异的非易失性半导体存储器件，包括在形成有间隔的一对杂质区域之间形成沟道形成区域的半导体衬底和第一绝缘层，浮置栅极，第二栅极 绝缘层和位于半导体衬底的上层部分上的控制栅极。 形成浮栅的半导体材料的带隙优选比半导体基板的带隙小。 例如，形成浮置栅极的半导体材料的带隙优选比半导体衬底中的沟道形成区域的带隙小0.1eV以上。 这是因为，通过将浮置栅电极的导带的底部能量水平降低到半导体衬底中的沟道形成区域的底部能级，能够提高载流子注入和电荷保持特性。

公开(公告)号：US20070235793A1

公开(公告)日：2007-10-11

申请号：US11723483

申请日：2007-03-20

申请人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

发明人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1214 ,  H01L29/7881

摘要： It is an object to provide a nonvolatile semiconductor memory device having excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate, a second insulating layer, and a control gate are provided. The floating gate has at least a two-layer structure, and a first layer in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. Furthermore, by setting an energy level at the bottom of the conduction band of the floating gate lower than that of the channel forming region of the semiconductor layer, injectability of carriers and a charge-retention property can be improved.

摘要翻译： 本发明的目的是提供具有优异的书写特性和电荷保持性的非易失性半导体存储器件。 提供了包括形成为彼此分开的一对杂质区之间的沟道形成区域的半导体层。 在其上层部分中，设置有第一绝缘层，浮栅，第二绝缘层和控制栅。 浮栅具有至少两层结构，与第一绝缘层接触的第一层优选具有比半导体层小的带隙。 此外，通过将浮置栅极的导带的底部的能级设定为低于半导体层的沟道形成区的能级，能够提高载流子的注入性和电荷保持性。

公开(公告)号：US20070228453A1

公开(公告)日：2007-10-04

申请号：US11725487

申请日：2007-03-20

申请人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

发明人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7883

摘要： An object is to provide a nonvolatile semiconductor memory device which is superior in writing property and charge holding property. A semiconductor substrate in which a channel formation region is formed between a pair of impurity regions is provided, and a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided over the semiconductor substrate. The floating gate electrode includes at least two layers. It is preferable that a band gap of a first floating gate electrode, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. It is also preferable that a second floating gate electrode be formed of a metal material, an alloy material, or a metal compound material. This is because, by lowering the bottom energy level of a conduction band of the floating gate electrode than that of the channel formation region in the semiconductor substrate, a carrier injecting property and a charge holding property can be improved.

摘要翻译： 本发明的目的是提供一种写入性和电荷保持性优异的非易失性半导体存储器件。 提供了在一对杂质区域之间形成沟道形成区域的半导体衬底，并且在半导体衬底上设置有第一绝缘层，浮栅电极，第二绝缘层和控制栅电极。 浮栅电极包括至少两层。 优选与第一绝缘层接触的第一浮栅的带隙小于半导体基板的带隙。 另外，优选第二浮栅电极由金属材料，合金材料或金属复合材料形成。 这是因为，通过降低浮置栅极的导带的底部能量水平比半导体衬底中的沟道形成区域的底部能量水平降低，可以提高载流子注入性和电荷保持性。

公开(公告)号：US20070228448A1

公开(公告)日：2007-10-04

申请号：US11723506

申请日：2007-03-20

申请人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

发明人： Shunpei Yamazaki ,  Yoshinobu Asami ,  Tamae Takano ,  Makoto Furuno

IPC分类号： H01L29/76

CPC分类号： H01L27/1237 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1214 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885

摘要： It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided. The floating gate has at least a two-layer structure, and a first layer being in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. The stability of the first layer is improved by formation of a second layer of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.

摘要翻译： 本发明的目的是提供具有优异的书写特性和电荷保持性的非易失性半导体存储器件。 提供了包括形成为彼此分开的一对杂质区之间的沟道形成区域的半导体层。 在其上层部分中，设置有第一绝缘层，浮栅电极，第二绝缘层和控制栅电极。 浮栅具有至少两层结构，与第一绝缘层接触的第一层优选具有比半导体层的带隙小的带隙。 通过使用金属，合金或金属复合材料形成第二层浮栅电极来改善第一层的稳定性。 浮栅电极的这种结构可以改善载体在书写中的注入性和电荷保持性。