公开(公告)号：US06754126B2

公开(公告)日：2004-06-22

申请号：US10106597

申请日：2002-03-27

申请人： Shusaku Yamaguchi ,  Toshiya Uchida ,  Yoshimasa Yagishita ,  Yoshihide Bando ,  Masahiro Yada ,  Masaki Okuda ,  Hiroyuki Kobayashi ,  Kota Hara ,  Shinya Fujioka ,  Waichiro Fujieda

发明人： Shusaku Yamaguchi ,  Toshiya Uchida ,  Yoshimasa Yagishita ,  Yoshihide Bando ,  Masahiro Yada ,  Masaki Okuda ,  Hiroyuki Kobayashi ,  Kota Hara ,  Shinya Fujioka ,  Waichiro Fujieda

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4087 ,  G11C2211/4061 ,  G11C2211/4062

摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

摘要翻译： 形成多个第一存储块和用于再现第一存储块的数据的第二存储块。 当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。 当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。 因此，可以在不被用户识别的情况下进行刷新操作。 即，可以提供用户友好的半导体存储器。

公开(公告)号：US06266294B1

公开(公告)日：2001-07-24

申请号：US09304516

申请日：1999-05-04

申请人： Masahiro Yada ,  Hiroyoshi Tomita

发明人： Masahiro Yada ,  Hiroyoshi Tomita

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/22

摘要： According to the present invention, in an integrated circuit device for receiving an external clock signal and a clock enable signal and for supplying to an internal circuit an internal clock signal which has a predetermined phase relationship with the external clock signal, a DLL circuit for generating a delay clock signal, synchronized and in phase with the external clock signal, is operated continuously even in a low power consumption mode, and the provision of the delay clock signal to the internal circuit is halted. When the mode is switched from the low power consumption mode to the normal mode, the delay clock signal generated by the DLL circuit, which is operated continuously, is supplied as an internal clock signal to the internal circuit again.

摘要翻译： 根据本发明，在用于接收外部时钟信号和时钟使能信号并用于向内部电路提供与外部时钟信号具有预定相位关系的内部时钟信号的集成电路装置中，用于产生 与外部时钟信号同步且同相的延迟时钟信号即使在低功耗模式下也连续工作，并且停止向内部电路提供延迟时钟信号。 当模式从低功耗模式切换到正常模式时，由连续操作的DLL电路产生的延迟时钟信号作为内部时钟信号被再次提供给内部电路。