公开(公告)号：US20100205306A1

公开(公告)日：2010-08-12

申请号：US12702857

申请日：2010-02-09

申请人： Hiroshi Kayanuma ,  Kouitirou Takahasi ,  Masaki Okuda

发明人： Hiroshi Kayanuma ,  Kouitirou Takahasi ,  Masaki Okuda

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F15/173

CPC分类号： G06F9/505 ,  G06F9/5094 ,  G06F2209/5019 ,  Y02D10/22

摘要： A grid computing system includes a plurality of nodes for processing a plurality of jobs, and a management apparatus for managing the plurality of the nodes. Each of the nodes is switchable between a standby and an active status, respectively. And the management apparatus including, a job request unit for allotting a plurality of requests of jobs to any of the nodes in an active state, a prediction unit for predicting the number of the nodes in the active state optimal for predicted amount of jobs requested from the exterior at a future time when a predetermined time period lapses from the present time, and a controller for controlling switching of the nodes between the standby and active so as to control the predicted number of the nodes to start switching before the future time.

摘要翻译： 网格计算系统包括用于处理多个作业的多个节点，以及用于管理多个节点的管理装置。 每个节点分别在待机状态和活动状态之间切换。 并且，所述管理装置包括：作业请求单元，用于将多个作业请求分配给处于活动状态的任何节点;预测单元，用于预测所述活动状态中的节点数目， 在从当前时间经过预定时间段的未来时间的外部，以及控制器，用于控制备用和活动之间的节点的切换，以便控制节点的预测数量在未来时间之前开始切换。

公开(公告)号：US20080246540A1

公开(公告)日：2008-10-09

申请号：US11878748

申请日：2007-07-26

申请人： Masaki Okuda

发明人： Masaki Okuda

IPC分类号： H01L25/00

CPC分类号： H01L27/0682

摘要： A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential, and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the one or more wells and connected to a first diffusion layer of the one or more diffusion layers that is formed in the first well.

摘要翻译： 半导体集成电路包括半导体衬底，形成在半导体衬底中的一个或多个阱，形成在一个或多个阱中的一个或多个扩散层，形成在互连层中的多个互连，一个或多个扩散层和 多个互连串联连接以提供第一电位和第二电位之间的耦合，以及比较电路，其耦合到设置在第一电位和第二电位之间的第三电位的互连中的一个，并且被配置为将第三电位 具有参考电位的电位，其中被设置为第一电位的多个互连的第一互连连接到所述一个或多个阱的至少第一阱并连接到所述一个或多个扩散层的第一扩散层 这是在第一口井中形成的。

公开(公告)号：US07642844B2

公开(公告)日：2010-01-05

申请号：US11878748

申请日：2007-07-26

申请人： Masaki Okuda

发明人： Masaki Okuda

IPC分类号： H01L25/00

CPC分类号： H01L27/0682

摘要： A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential, and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the one or more wells and connected to a first diffusion layer of the one or more diffusion layers that is formed in the first well.

摘要翻译： 半导体集成电路包括半导体衬底，形成在半导体衬底中的一个或多个阱，形成在一个或多个阱中的一个或多个扩散层，形成在互连层中的多个互连，一个或多个扩散层和 多个互连串联连接以提供第一电位和第二电位之间的耦合，以及比较电路，其耦合到设置在第一电位和第二电位之间的第三电位的互连中的一个，并且被配置为将第三电位 具有参考电位的电位，其中被设置为第一电位的多个互连的第一互连连接到所述一个或多个阱的至少第一阱并连接到所述一个或多个扩散层的第一扩散层 这是在第一口井中形成的。

公开(公告)号：US20090040850A1

公开(公告)日：2009-02-12

申请号：US12130480

申请日：2008-05-30

申请人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

发明人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/48 ,  G11C2029/1802

摘要： An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.

摘要翻译： 地址开关电路接收提供给第一地址端子组的行地址信号和提供给第二地址端子组的列地址信号。 此外，地址开关电路接收提供给第二地址端子组的行地址信号，然后接收提供给第二地址端子组的列地址信号，并将接收到的行地址信号和接收的列地址信号提供给行解码器， 列解码器在第二操作模式期间。 可以通过在第二操作模式下执行半导体存储器的操作测试来增加一次测试的半导体存储器的数量。 此外，可以使用用于其他半导体存储器的测试资产来测试半导体存储器。 因此，可以提高测试效率，并且可以降低测试成本。

公开(公告)号：US07330062B2

公开(公告)日：2008-02-12

申请号：US11643888

申请日：2006-12-22

申请人： Hiroyuki Kobayashi ,  Masaki Okuda

发明人： Hiroyuki Kobayashi ,  Masaki Okuda

IPC分类号： H03H11/16

CPC分类号： H03K5/1515 ,  H03K5/26 ,  H03K19/00323 ,  H03K19/21 ,  H03L7/0812 ,  H03L7/089

摘要： A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

摘要翻译： 逻辑电路接收第一和第二输入信号，其中第一逻辑电平的周期部分地重叠，并输出其中第一逻辑电平的周期不重叠的第一和第二输出信号。 逻辑电路包括第一单元，当从第二逻辑电平到第一逻辑电平的第一输入信号的改变被检测到时，将第一输出信号的相位从第二逻辑电平改变到第一逻辑电平。 当检测到第一输入信号的变化时，第二输入信号被检测为处于第一逻辑电平时，第二单元将第二输出信号的相位从第一逻辑电平改变为第二逻辑电平。

公开(公告)号：US20070103218A1

公开(公告)日：2007-05-10

申请号：US11643888

申请日：2006-12-22

申请人： Hiroyuki Kobayashi ,  Masaki Okuda

发明人： Hiroyuki Kobayashi ,  Masaki Okuda

IPC分类号： H03K5/13

CPC分类号： H03K5/1515 ,  H03K5/26 ,  H03K19/00323 ,  H03K19/21 ,  H03L7/0812 ,  H03L7/089

摘要： A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

公开(公告)号：US20060174013A1

公开(公告)日：2006-08-03

申请号：US11236624

申请日：2005-09-28

申请人： Akira Katsumata ,  Masaki Okuda

发明人： Akira Katsumata ,  Masaki Okuda

IPC分类号： G06F15/16

CPC分类号： H04L67/06 ,  H04L41/06 ,  H04L43/0811

摘要： In a data transfer method for transfer of data by a first information processing terminal device to a second information processing terminal device connected to the first information processing terminal device via a signal line, the first information processing terminal device calculates a maximum required time according to the amount of data for transfer and transfer performance information relating to the connection of the first information processing terminal device with the second information processing terminal device; upon initiating the data transfer processing, the first information processing terminal device continuously confirms that the data transfer processing is in state of execution from the time of initiation of the data transfer processing until the maximum required time has elapsed; and if, when the maximum required time has elapsed, the data transfer processing initiated is confirmed to be continuing, the first information processing terminal device forcibly ends the data transfer processing.

摘要翻译： 在通过第一信息处理终端装置将数据传送到经由信号线与第一信息处理终端装置连接的第二信息处理终端装置的数据传送方法中，第一信息处理终端装置根据 与第一信息处理终端装置与第二信息处理终端装置的连接有关的传送和传送性能信息的数据量; 在开始数据传送处理时，第一信息处理终端装置从数据传送处理开始直到最长所需时间过去，连续确认数据传送处理处于执行状态; 并且如果当最大所需时间已经过去时，确认发起的数据传送处理继续进行，则第一信息处理终端装置强制结束数据传送处理。

公开(公告)号：US06728157B2

公开(公告)日：2004-04-27

申请号：US10335948

申请日：2003-01-03

申请人： Yoshimasa Yagishita ,  Toshiya Uchida ,  Yoshihide Bando ,  Hiroyuki Kobayashi ,  Shusaku Yamaguchi ,  Masaki Okuda

发明人： Yoshimasa Yagishita ,  Toshiya Uchida ,  Yoshihide Bando ,  Hiroyuki Kobayashi ,  Shusaku Yamaguchi ,  Masaki Okuda

IPC分类号： G11C700

CPC分类号： G11C11/4087 ,  G11C11/406

摘要： A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

公开(公告)号：US06337833B1

公开(公告)日：2002-01-08

申请号：US09346919

申请日：1999-07-02

申请人： Kazuyuki Kanazashi ,  Toshiya Uchida ,  Masaki Okuda

发明人： Kazuyuki Kanazashi ,  Toshiya Uchida ,  Masaki Okuda

IPC分类号： G11C800

CPC分类号： G11C7/225 ,  G11C7/1051 ,  G11C7/1072

摘要： One aspect of the present invention is that, when the memory is in the non-power-down state, the supply of clock signals to the data output circuit is limited to the read status after the reception of a read command, and no clock signal supply is performed when either the active status or the write status is in effect. In the best aspect, furthermore, in the read status after the reception of a read command, the supply of clock signals to the data output circuit starts after a number of clock signals corresponding to a set CAS latency following the read command, and stops after a number of clock signals corresponding to a set burst length, after the output of the read out data from the data output circuit starts. Accordingly, even in the non-power-down state, clock signals are only supplied during the time required for the read out data to be actually output from the data output circuit to the outside, whereby it is possible to reduce the number of clock signal supply actions that require large current drive.

摘要翻译： 本发明的一个方面是，当存储器处于非掉电状态时，向数据输出电路提供时钟信号被限制在接收到读命令之后的读状态，并且没有时钟信号 当活动状态或写入状态都有效时执行供电。 此外，在最佳方面，在接收到读取命令之后的读取状态下，在与读取命令之后的设定的CAS延迟相对应的多个时钟信号之后，向数据输出电路提供时钟信号开始，并且在后面停止 在从数据输出电路输出读出数据开始之后，与设定的突发长度对应的多个时钟信号。 因此，即使在非掉电状态下，时钟信号仅在从数据输出电路向外部输出的读出数据所需的时间内提供，从而可以减少时钟信号的数量 提供需要大电流驱动的动作。

公开(公告)号：US20100112353A1

公开(公告)日：2010-05-06

申请号：US12450704

申请日：2008-03-31

申请人： Ren-de Sun ,  Kiyoto Matsushita ,  Taku Sasaki ,  Shinya Uenoyama ,  Masaki Okuda ,  Nobuyuki Okinaga

发明人： Ren-de Sun ,  Kiyoto Matsushita ,  Taku Sasaki ,  Shinya Uenoyama ,  Masaki Okuda ,  Nobuyuki Okinaga

IPC分类号： B32B15/02

CPC分类号： H05K3/323 ,  B23K35/262 ,  B23K2101/36 ,  C23C18/1635 ,  C23C18/1653 ,  C23C18/1692 ,  C23C18/30 ,  C23C18/34 ,  C23C18/54 ,  H01L24/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29311 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01R13/03 ,  H05K2201/0221 ,  H05K2203/0425 ,  Y10T428/2982 ,  Y10T428/2998 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

摘要： It is an object of the present invention to provide: a conductive fine particle, which is used for conductive connection between fine electrodes and tends not to give rise to a crack in the solder layer or disconnection caused by breakage in the connection interface between an electrode and the conductive fine particle even with a drop impact and the like, and tends not to have fatigue even after repetitive heating and cooling; an anisotropic conductive material obtained by using the conductive fine particle; and a conductive connection structure.The present invention relates to a conductive fine particle, which comprises a solder layer containing tin and being formed on a surface of a resin fine particle, with nickel adhered to a surface of the solder layer, and contains 0.0001 to 5.0% by weight of the nickel with respect to a total of a metal contained in the solder layer and the nickel adhered to the surface of the solder layer.

摘要翻译： 本发明的目的是提供：导电性微粒，用于在细电极之间进行导电连接，并且不会引起焊料层中的裂纹或由电极之间的连接界面中的断裂引起的断开 导电性细颗粒即使具有液滴冲击等，并且即使在重复加热和冷却之后也不会有疲劳; 通过使用导电性微粒获得的各向异性导电材料; 和导电连接结构。 本发明涉及一种导电性细颗粒，其包含含锡的焊料层，并且形成在树脂细颗粒的表面上，镍附着在焊料层的表面上，并且含有0.0001至5.0重量％的 镍相对于焊料层中包含的总量和附着到焊料层表面的镍。