公开(公告)号：US06754126B2

公开(公告)日：2004-06-22

申请号：US10106597

申请日：2002-03-27

申请人： Shusaku Yamaguchi ,  Toshiya Uchida ,  Yoshimasa Yagishita ,  Yoshihide Bando ,  Masahiro Yada ,  Masaki Okuda ,  Hiroyuki Kobayashi ,  Kota Hara ,  Shinya Fujioka ,  Waichiro Fujieda

发明人： Shusaku Yamaguchi ,  Toshiya Uchida ,  Yoshimasa Yagishita ,  Yoshihide Bando ,  Masahiro Yada ,  Masaki Okuda ,  Hiroyuki Kobayashi ,  Kota Hara ,  Shinya Fujioka ,  Waichiro Fujieda

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4087 ,  G11C2211/4061 ,  G11C2211/4062

摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

摘要翻译： 形成多个第一存储块和用于再现第一存储块的数据的第二存储块。 当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。 当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。 因此，可以在不被用户识别的情况下进行刷新操作。 即，可以提供用户友好的半导体存储器。

公开(公告)号：US06728157B2

公开(公告)日：2004-04-27

申请号：US10335948

申请日：2003-01-03

申请人： Yoshimasa Yagishita ,  Toshiya Uchida ,  Yoshihide Bando ,  Hiroyuki Kobayashi ,  Shusaku Yamaguchi ,  Masaki Okuda

发明人： Yoshimasa Yagishita ,  Toshiya Uchida ,  Yoshihide Bando ,  Hiroyuki Kobayashi ,  Shusaku Yamaguchi ,  Masaki Okuda

IPC分类号： G11C700

CPC分类号： G11C11/4087 ,  G11C11/406

摘要： A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

公开(公告)号：US6104659A

公开(公告)日：2000-08-15

申请号：US338599

申请日：1999-06-23

申请人： Yoshimasa Yagishita ,  Toshiya Uchida ,  Masaki Okuda

发明人： Yoshimasa Yagishita ,  Toshiya Uchida ,  Masaki Okuda

IPC分类号： G11C11/413 ,  G05F1/00 ,  G11C5/14 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C5/143 ,  G11C5/147

摘要： A memory device comprises: a plurality of banks each of which includes an array of memory cells; and at least a first and a second internal power generator, provided for each of the plurality of banks, for generating an internal power source voltage which differs from a voltage supplied by an external power source. If the internal common power source voltage in the memory device is lower than the first voltage when the power is on, the first and the second internal power generators in a plurality of banks are activated so as to rapidly raise the common internal power source voltage. When the common internal power source voltage in the memory device is higher than the first voltage and lower than the second voltage, the second internal power generators in the banks are activated to compensate for a drop in the internal power source voltage, which is caused by current leakage. When the internal power source voltage in a bank in the activated state is lower than the third voltage, the first and the second internal power generators in the corresponding bank are activated and satisfactorily drive the internal power source voltage in the bank so as to operate the memory device at a high speed.

摘要翻译： 存储器件包括：多个存储体，每个存储体包括存储器单元的阵列; 以及为多个组中的每一个提供的至少第一和第二内部发电机，用于产生不同于由外部电源提供的电压的内部电源电压。 如果在电源接通时存储器件内部的公共电源电压低于第一电压，则多个组中的第一和第二内部发电机被激活，以便迅速提高公共内部电源电压。 当存储器件中的公共内部电源电压高于第一电压并低于第二电压时，该组中的第二内部发电机被激活以补偿内部电源电压的下降，这是由 电流泄漏。 当处于激活状态的组中的内部电源电压低于第三电压时，相应组中的第一和第二内部发电机被激活并令人满意地驱动组中的内部电源电压，以便操作 高速存储设备。

公开(公告)号：US06987698B2

公开(公告)日：2006-01-17

申请号：US10289314

申请日：2002-11-07

申请人： Yoshihide Bando ,  Yoshimasa Yagishita

发明人： Yoshihide Bando ,  Yoshimasa Yagishita

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory cell array is partitioned into a plurality of memory regions each of which includes a plurality of sense amplifiers and each of which is established as a unit of data input/output. Dummy regions each are formed between every two memory regions and include dummy bit lines that are set to a predetermined voltage at least during the operation of the memory cell array. Since the dummy bit lines are wired between the bit lines of the two adjacent memory regions, the voltage change in the bit lines in any of the memory regions can be prevented from affecting the bit lines in the other memory regions. As a result, malfunction of semiconductor memories can be prevented.

摘要翻译： 存储单元阵列被划分成多个存储区域，每个存储器区域包括多个读出放大器，并且每个存储单元被建立为数据输入/输出的单元。 至少在存储单元阵列的操作期间，每两个存储区域之间形成虚拟区域，并且包括设置为预定电压的虚拟位线。 由于虚拟位线被布线在两个相邻的存储区域的位线之间，因此可以防止任何存储区域中的位线中的电压变化影响其它存储区域中的位线。 结果，可以防止半导体存储器的故障。

公开(公告)号：US06629224B1

公开(公告)日：2003-09-30

申请号：US09562739

申请日：2000-05-01

申请人： Takaaki Suzuki ,  Toshiya Uchida ,  Kotoku Sato ,  Yoshimasa Yagishita

发明人： Takaaki Suzuki ,  Toshiya Uchida ,  Kotoku Sato ,  Yoshimasa Yagishita

IPC分类号： G06F1200

CPC分类号： G11C11/406 ,  G11C5/066 ,  G11C11/40603 ,  G11C11/40611

摘要： Signals supplied to predetermined terminals are accepted as commands at a plurality of times, the number of operating modes is sequentially narrowed down based on the command each time and an internal circuit is controlled according to the narrowed operating modes. Since the information necessary for determining an operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be required so that the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size. The command controlling circuit with a plurality of accepting circuits is comprised. Each of the accepting circuits respectively accepts signals, supplied at a plurality of times, each time. In other words, in accordance with the timing of the signal supplement, a different accepting circuit is respectively operated and the internal circuit is controlled. Accordingly, a command controlling circuit may be readily designed even in the semiconductor memory device having a complicated command combination. Consequently, it is able to facilitate the verification of the design.

摘要翻译： 提供给预定端子的信号被多次接受为命令，每次基于该命令并且根据变窄的操作模式控制内部电路，操作模式的数量依次变窄。 由于多次接受确定操作模式所需的信息，因此可以减少输入命令所需的终端数量。 特别地，在专用端子输入命令的情况下，不再需要其输入焊盘，输入电路等，从而可以减小芯片尺寸。 通过减少端子数量来实现减少，这限制了封装尺寸。 包括具有多个接受电路的指令控制电路。 每个接收电路分别接收每次多次提供的信号。 换句话说，根据信号补充的定时，分别操作不同的接受电路，并且控制内部电路。 因此，即使在具有复杂的指令组合的半导体存储器件中，也可以容易地设计指令控制电路。 因此，它能够方便验证设计。

公开(公告)号：US06525570B2

公开(公告)日：2003-02-25

申请号：US09820719

申请日：2001-03-30

申请人： Yoshimasa Yagishita ,  Toshiya Uchida

发明人： Yoshimasa Yagishita ,  Toshiya Uchida

IPC分类号： H03K190175

CPC分类号： H03K19/0002 ,  H03K19/017509

摘要： The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.

公开(公告)号：US06999358B2

公开(公告)日：2006-02-14

申请号：US10671473

申请日：2003-09-29

申请人： Yoshimasa Yagishita ,  Toshiya Uchida

发明人： Yoshimasa Yagishita ,  Toshiya Uchida

IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C8/00 ,  G11C5/06

CPC分类号： G11C29/80 ,  G11C29/848

摘要： A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.

公开(公告)号：US06876225B2

公开(公告)日：2005-04-05

申请号：US10178559

申请日：2002-06-25

申请人： Yoshimasa Yagishita ,  Toshiya Uchida

发明人： Yoshimasa Yagishita ,  Toshiya Uchida

IPC分类号： G06F3/00 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/20 ,  H03K17/16

CPC分类号： H03K19/0002 ,  H03K19/017509

摘要： The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.

摘要翻译： 发射机中的电流产生单元根据多个逻辑值产生输出电流。 接收器中的参考电流产生单元产生多个参考电流。 接收器中的当前比较单元分别将参考电流与来自发射器的输出电流进行比较，并恢复逻辑值。 也就是说，电流根据从发射机发送到接收机的逻辑值而变化，其中根据当前值的差异在接收机中恢复逻辑值。 在接收机中形成多个电流比较单元使得可以容易地比较来自发射器的输出电流和多个参考电流的值。 因此，可以容易地增加多值比特的数量，以便构成高比特率多值输入/输出接口。

公开(公告)号：US06696859B2

公开(公告)日：2004-02-24

申请号：US10178519

申请日：2002-06-25

申请人： Yoshimasa Yagishita ,  Toshiya Uchida

发明人： Yoshimasa Yagishita ,  Toshiya Uchida

IPC分类号： H03K190175

CPC分类号： H03K19/0002 ,  H03K19/017509

摘要： The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.

摘要翻译： 发射机中的电流产生单元根据多个逻辑值产生输出电流。 接收器中的参考电流产生单元产生多个参考电流。 接收器中的当前比较单元分别将参考电流与来自发射器的输出电流进行比较，并恢复逻辑值。 也就是说，电流根据从发射机发送到接收机的逻辑值而变化，其中根据当前值的差异在接收机中恢复逻辑值。 在接收机中形成多个电流比较单元使得可以容易地比较来自发射器的输出电流和多个参考电流的值。 因此，可以容易地增加多值比特的数量，以便构成高比特率多值输入/输出接口。

公开(公告)号：US06654298B2

公开(公告)日：2003-11-25

申请号：US09988614

申请日：2001-11-20

申请人： Yoshimasa Yagishita ,  Toshiya Uchida

发明人： Yoshimasa Yagishita ,  Toshiya Uchida

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  G11C29/848

摘要： A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.