公开(公告)号：US20130270613A1

公开(公告)日：2013-10-17

申请号：US13447311

申请日：2012-04-16

申请人： Shyan-Liang Chou ,  Tsung-Min Kuo ,  Po-Wen Su ,  Chun-Mao Chiou ,  Feng-Mou Chen

发明人： Shyan-Liang Chou ,  Tsung-Min Kuo ,  Po-Wen Su ,  Chun-Mao Chiou ,  Feng-Mou Chen

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843

摘要： A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.

摘要翻译： 修整间隔物的方法包括在形成最外层间隔物时蚀刻氧化硅间隔物，使得接触栅电极的硅氮化物间隔物露出一个区域。 然后可以通过磷酸将部分地除去硅氮化硅间隔物的暴露面积。 在半导体工艺结束时，硅碳氮化物间隔物的顶表面的至少一部分将低于栅电极的顶表面。

公开(公告)号：US08975673B2

公开(公告)日：2015-03-10

申请号：US13447311

申请日：2012-04-16

申请人： Shyan-Liang Chou ,  Tsung-Min Kuo ,  Po-Wen Su ,  Chun-Mao Chiou ,  Feng-Mou Chen

发明人： Shyan-Liang Chou ,  Tsung-Min Kuo ,  Po-Wen Su ,  Chun-Mao Chiou ,  Feng-Mou Chen

IPC分类号： H01L29/76 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843

摘要： A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.

摘要翻译： 修整间隔物的方法包括在形成最外层间隔物时蚀刻氧化硅间隔物，使得接触栅电极的硅氮化物间隔物露出一个区域。 然后可以通过磷酸将部分地除去硅氮化硅间隔物的暴露面积。 在半导体工艺结束时，硅碳氮化物间隔物的顶表面的至少一部分将低于栅电极的顶表面。

公开(公告)号：US08524556B1

公开(公告)日：2013-09-03

申请号：US13419437

申请日：2012-03-14

申请人： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

发明人： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629

摘要： A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

摘要翻译： 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

公开(公告)号：US20130241002A1

公开(公告)日：2013-09-19

申请号：US13419437

申请日：2012-03-14

申请人： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

发明人： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0629

摘要： A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

摘要翻译： 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。