公开(公告)号：US20240354253A1

公开(公告)日：2024-10-24

申请号：US18758994

申请日：2024-06-28

Applicant: SIFive, Inc.

Inventor： Binayak Tiwari ,  Benoy Alexander ,  John Ingallis ,  Mohit Gupta

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: Described is a system and method for implementing a prefetcher with an out-of-order filtered prefetcher training queue. A processing system includes a prefetcher and a prefetcher training queue connected to the prefetcher. The prefetcher training queue configured to receive one or more demand requests from one or more load-store units, allocate a prefetcher training queue entry for a non-duplicative demand request, and send, to the prefetcher, a stored demand request together with a hit or miss indicator, wherein the prefetcher training queue sends stored demand requests without regard to program order.

公开(公告)号：US20240338219A1

公开(公告)日：2024-10-10

申请号：US18747412

申请日：2024-06-18

Applicant: SiFive, Inc.

Inventor： Paul Walmsley ,  John Ingalls ,  Benoy Alexander

IPC: G06F9/38

CPC classification number: G06F9/3802

Abstract: Disclosed are systems and methods for configuring a prefetcher. A process may reconfigure a prefetcher associated with a processor core responsive to a context switch. The context switch may comprise the processor core changing from executing a first process to a second process. In some implementations, reconfiguring the prefetcher may include updating a register controlling an operation of the prefetcher from a first set of parameters associated with the first process to a second set of parameters associated with the second process. In some implementations, the second set of parameters may be based on input from a process executed in a user mode.

公开(公告)号：US20240184581A1

公开(公告)日：2024-06-06

申请号：US18497170

申请日：2023-10-30

Applicant: SiFive, Inc.

Inventor： Benoy Alexander ,  John Ingalls ,  Binayak Tiwari

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30047 ,  G06F9/3816 ,  G06F9/3836

Abstract: Described herein is a bit pattern matching hardware prefetcher which captures complex repeating patterns, allows out-of-order (OOO) training, and allows OOO confirmations. The prefetcher includes a plurality of prefetch engines. Each prefetch engine is associated with a zone, each zone has a plurality of subzones, and each subzone has a plurality of cache lines. The prefetcher includes an access map for each subzone. Each bit position represents a cache line in the plurality of cache lines. The prefetcher determines whether a demand request matches one of the plurality of prefetch engines, updates, with respect to the demand request, a bit position in an access map for a subzone in a matching prefetch engine, determines a pattern from an access map for a subzone when a defined number of demand requests have been matched to the subzone; and generates a prefetch request based on at least the determined pattern.

公开(公告)号：US20230418763A1

公开(公告)日：2023-12-28

申请号：US18203186

申请日：2023-05-30

Applicant: SiFive, Inc.

Inventor： Benoy Alexander ,  John Ingalls ,  Mohit Gopal Wani

IPC: G06F12/1036

CPC classification number: G06F12/1036 ,  G06F2212/681 ,  G06F2212/684

Abstract: Described is a translation lookaside buffer (TLB) prefetcher with multi-level TLB prefetches and feedback architecture. A processing system includes two or more translation lookaside buffer (TLB) levels, each TLB level including a miss queue, and a TLB prefetcher connected to each of the two or more TLB levels. The TLB prefetcher configured to receive feedback from the miss queue at each TLB level for previously sent TLB prefetches and control number of TLB prefetches sent for a trained TLB entry to each TLB level of the two or more TLB levels based on the feedback.