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    Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield
    1.
    发明授权
    Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield 有权
    低噪声电感使用电浮动高电阻和接地的低电阻图案屏蔽

    公开(公告)号：US06777774B2

    公开(公告)日：2004-08-17

    申请号：US10125244

    申请日：2002-04-17

    申请人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

    发明人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

    IPC分类号： H01L2900

    CPC分类号： H01L28/10 ,  H01L23/552 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.

    摘要翻译： 公开了一种半导体上的新型有用屏蔽电感器。 电浮动高电阻材料的区域沉积在电感器和半导体衬底之间。 高电阻屏蔽层被图案化为多个间隙，使得由电感器在屏蔽层中感应的电流不具有闭环路径。 高电阻浮动屏蔽补充了接地的低电阻屏蔽以实现更高性能的电感器。 以这种方式，衬底中的噪声降低。 新型互补屏蔽不会显着降低电感器的品质因数，如品质因数和谐振频率。 在一个实施例中，接地屏蔽由图案化的N阱（或P阱）结构制成。 在另一个实施例中，低电阻电接地屏蔽由图案化的硅化物制成，其可以形成在衬底本身的部分上。

    Silicon-based inductor with varying metal-to-metal conductor spacing
    2.
    发明授权
    Silicon-based inductor with varying metal-to-metal conductor spacing 失效
    具有不同金属 - 金属导体间距的硅基电感器

    公开(公告)号：US06714112B2

    公开(公告)日：2004-03-30

    申请号：US10144542

    申请日：2002-05-10

    申请人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu

    发明人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu

    IPC分类号： H01F500

    CPC分类号： H01F17/0006 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A silicon-based inductor in a semiconductor is disclosed. One embodiment provides for an inductor having a metal region comprising turns. The metal region has spacing between adjacent turns. The width of the spacing varies. The spacing is pre-determined to optimize the performance of the inductor by reducing eddy currents in the turns and reducing eddy currents induced in a substrate. One embodiment provides for an inductor having a spiral structure. The spiral structure may have a number of turns with the spacing between the turns of the inductor being larger near the inside of the spiral structure. A large spacing between the inductor's inner turns may serve to reduce both conductor eddy currents and the induced substrate current. Thus, the structure improves the inductor's overall performance.

    摘要翻译： 公开了半导体中的硅基电感器。 一个实施例提供了具有包括匝的金属区域的电感器。 金属区域在相邻的匝之间具有间隔。 间距的宽度变化。 通过减小匝中的涡电流并减少在衬底中感应的涡电流，预先确定间距以优化电感器的性能。 一个实施例提供具有螺旋结构的电感器。 螺旋结构可以具有多个匝数，在螺旋结构的内部附近，电感器匝之间的间距更大。 电感器内圈之间的大间距可用于减少导体涡流和感应衬底电流。 因此，该结构提高了电感器的整体性能。

    Method of reducing substrate coupling for chip inductors by creation of dielectric islands by selective EPI deposition
    4.
    发明授权
    Method of reducing substrate coupling for chip inductors by creation of dielectric islands by selective EPI deposition 有权
    通过选择性EPI沉积形成介质岛来减少芯片电感器的衬底耦合的方法

    公开(公告)号：US06486017B1

    公开(公告)日：2002-11-26

    申请号：US10161772

    申请日：2002-06-04

    申请人： Purakh Raj Verma ,  Sanford Chu ,  Johnny Chew ,  Sia Choon Beng

    发明人： Purakh Raj Verma ,  Sanford Chu ,  Johnny Chew ,  Sia Choon Beng

    IPC分类号： H01L218234

    CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L27/08

    摘要： A new method is provided for the creation of a horizontal spiral inductor over the surface of a silicon substrate. A first layer of dielectric is deposited over the surface of the substrate, this first layer of dielectric is patterned and etched creation islands of first dielectric material overlying the surface of the substrate, the islands of first dielectric material align with coils of a thereover to be created spiral inductor. The openings created in the layer of dielectric by the patterning and etching of the first layer of dielectric are filled by selective deposition of epitaxial silicon therein. Second and third layers of dielectric are successively deposited over the surface of the first layer of dielectric. A spiral horizontal inductor is then created over the surface of the third layer of dielectric.

    摘要翻译： 提供了一种新的方法，用于在硅衬底的表面上创建水平螺旋电感器。 电介质的第一层沉积在衬底的表面上，该第一层电介质被图案化并且蚀刻产生覆盖衬底表面的第一介电材料的岛，第一介电材料的岛与其上的线圈对准， 创建螺旋电感。 通过第一层电介质的图案化和蚀刻在电介质层中产生的开口通过在其中选择性沉积外延硅来填充。 第二和第三层电介质依次沉积在第一层电介质的表面上。 然后在第三层电介质的表面上形成螺旋水平电感器。