公开(公告)号：US06777774B2

公开(公告)日：2004-08-17

申请号：US10125244

申请日：2002-04-17

申请人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

发明人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

IPC分类号： H01L2900

CPC分类号： H01L28/10 ,  H01L23/552 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.

摘要翻译： 公开了一种半导体上的新型有用屏蔽电感器。 电浮动高电阻材料的区域沉积在电感器和半导体衬底之间。 高电阻屏蔽层被图案化为多个间隙，使得由电感器在屏蔽层中感应的电流不具有闭环路径。 高电阻浮动屏蔽补充了接地的低电阻屏蔽以实现更高性能的电感器。 以这种方式，衬底中的噪声降低。 新型互补屏蔽不会显着降低电感器的品质因数，如品质因数和谐振频率。 在一个实施例中，接地屏蔽由图案化的N阱（或P阱）结构制成。 在另一个实施例中，低电阻电接地屏蔽由图案化的硅化物制成，其可以形成在衬底本身的部分上。

公开(公告)号：US20050009357A1

公开(公告)日：2005-01-13

申请号：US10909523

申请日：2004-08-02

申请人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

发明人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

CPC分类号： H01L21/764 ,  H01L21/26506

摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

公开(公告)号：US07382027B2

公开(公告)日：2008-06-03

申请号：US11045958

申请日：2005-01-28

申请人： Purakh Raj Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Pradeep ,  Kai Shao ,  Jia Zhen Zheng

发明人： Purakh Raj Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Pradeep ,  Kai Shao ,  Jia Zhen Zheng

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76802 ,  H01L21/76829

摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.

摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

公开(公告)号：US06972237B2

公开(公告)日：2005-12-06

申请号：US10725670

申请日：2003-12-01

申请人： Purakh Raj Verma ,  Shao-fu Sanford Chu ,  Lap Chan ,  Jia Zhen Zheng ,  Jian Xun Li

发明人： Purakh Raj Verma ,  Shao-fu Sanford Chu ,  Lap Chan ,  Jia Zhen Zheng ,  Jian Xun Li

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

公开(公告)号：US20050136573A1

公开(公告)日：2005-06-23

申请号：US11045958

申请日：2005-01-28

申请人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

发明人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76802 ,  H01L21/76829

摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.

摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

公开(公告)号：US20050124131A1

公开(公告)日：2005-06-09

申请号：US11034932

申请日：2005-01-13

申请人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

发明人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

IPC分类号： H01F17/00 ,  H01L21/02 ,  H01L23/522 ,  H01L21/20 ,  H01L29/00

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

摘要翻译： 描述了在硅衬底上制造RF电感器件的方法。 沉积低k或其他电介质材料并图案化以形成电感器下板沟槽。 沟槽衬有阻挡膜，如填充有铜的TaN和使用化学机械抛光（CMP）平坦化的多余金属。 介电材料的第二层被沉积并图案化以形成通孔/沟槽。 通孔/沟槽图案填充有阻挡材料，蚀刻通孔/沟槽之间的电介质膜以形成第二组沟槽。 这些沟槽用铜填充并平坦化。 电介质膜的第三层被沉积并图案化以形成通孔/沟槽。 然后用阻挡材料填充通孔/沟槽，蚀刻通孔/沟槽图案之间的电介质膜以形成第三组沟槽。 这些沟槽填充有铜金属，并通过CMP去除多余的金属以形成所述RF电感器。

公开(公告)号：US06903013B2

公开(公告)日：2005-06-07

申请号：US10439923

申请日：2003-05-16

申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Yong Ju ,  Jia Zhen Zheng

发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Yong Ju ,  Jia Zhen Zheng

IPC分类号： H01L21/285 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/5227 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved method to deposit, by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors, has been developed. A process flow outlining the method of the present invention is as follows: (1) formation of trenches and channels, (2) atomic layer deposition of copper barrier and seed, (3) electroless deposition of copper, (4) chemical mechanical polishing back of excess copper, and (5) barrier deposition, SiN, forming copper interconnects and inductors.

摘要翻译： 已经开发了一种改进的方法，通过原子层沉积，ALD，用于化学镀铜的铜屏障和种子层，在镶嵌工艺中的填充沟槽和沟道或隧道开口，用于制造互连和电感器。 概述本发明方法的工艺流程如下：（1）形成沟槽和通道，（2）铜屏障和晶种的原子层沉积，（3）铜的无电沉积，（4）化学机械抛光 的过量铜，和（5）阻挡层沉积，SiN，形成铜互连和电感器。

公开(公告)号：US06638844B1

公开(公告)日：2003-10-28

申请号：US10207549

申请日：2002-07-29

申请人： Purakh Raj Verma ,  Sanford Chu ,  Chit Hwei ,  Lap Chan

发明人： Purakh Raj Verma ,  Sanford Chu ,  Chit Hwei ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L27/08 ,  H01L21/76224 ,  H01L21/823878 ,  H01L27/0617

摘要： A method of reducing substrate coupling and noise for one or more RFCMOS components comprising the following steps. A substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolation structures are formed within the substrate proximate the one or more RFCOMS components. The backside of the substrate is etched to form respective trenches within the substrate and over at least the one or more isolation structures. The respective trenches are filled with dielectric material whereby the substrate coupling and noise for the one or more RFCMOS components are reduced.

摘要翻译： 一种降低一个或多个RFCMOS组件的衬底耦合和噪声的方法，包括以下步骤。 提供具有前侧和背侧的基板。 在衬底上形成一个或多个RFCMOS部件。 一个或多个隔离结构在靠近一个或多个RFCOMS组件的衬底内形成。 蚀刻衬底的背面以在衬底内并且在至少一个或多个隔离结构上形成相应的沟槽。 相应的沟槽被电介质材料填充，由此降低了一个或多个RFCMOS部件的衬底耦合和噪声。

公开(公告)号：US07049201B2

公开(公告)日：2006-05-23

申请号：US10703297

申请日：2003-11-06

申请人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

发明人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.

摘要翻译： 一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个， 基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极 结构和收集器区域。 基底结构和发射极结构优选地形成在相同的处理室中。

公开(公告)号：US06924202B2

公开(公告)日：2005-08-02

申请号：US10683142

申请日：2003-10-09

申请人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

发明人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 提供了具有集电极区域的半导体衬底的异质结双极晶体管（HBT）及其制造方法。 基极接触层形成在集电极区域上，基底沟槽形成在基极接触层和集电极区域中。 在基底沟槽中形成具有侧壁部分和底部的本征基底结构。 在本征基底结构的侧壁部分上形成绝缘间隔物，并且在绝缘间隔物和本征基底结构的底部上形成发射极结构。 在基极接触层和发射极结构之上形成层间电介质层。 通过层间绝缘层到集电极区，基极接触层和发射极结构形成连接。 本征基础结构是硅和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。