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    Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield
    2.
    发明授权
    Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield 有权
    低噪声电感使用电浮动高电阻和接地的低电阻图案屏蔽

    公开(公告)号：US06777774B2

    公开(公告)日：2004-08-17

    申请号：US10125244

    申请日：2002-04-17

    申请人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

    发明人： Sia Choon Beng ,  Yeo Kiat Seng ,  Sanford Chu ,  Lap Chan ,  Chew Kok-Wai

    IPC分类号： H01L2900

    CPC分类号： H01L28/10 ,  H01L23/552 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.

    摘要翻译： 公开了一种半导体上的新型有用屏蔽电感器。 电浮动高电阻材料的区域沉积在电感器和半导体衬底之间。 高电阻屏蔽层被图案化为多个间隙，使得由电感器在屏蔽层中感应的电流不具有闭环路径。 高电阻浮动屏蔽补充了接地的低电阻屏蔽以实现更高性能的电感器。 以这种方式，衬底中的噪声降低。 新型互补屏蔽不会显着降低电感器的品质因数，如品质因数和谐振频率。 在一个实施例中，接地屏蔽由图案化的N阱（或P阱）结构制成。 在另一个实施例中，低电阻电接地屏蔽由图案化的硅化物制成，其可以形成在衬底本身的部分上。

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    5.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US07250669B2

    公开(公告)日：2007-07-31

    申请号：US10909523

    申请日：2004-08-02

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L29/00

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    6.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 失效
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US06869884B2

    公开(公告)日：2005-03-22

    申请号：US10225828

    申请日：2002-08-22

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。