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    Method of reducing substrate coupling for chip inductors by creation of dielectric islands by selective EPI deposition
    1.
    发明授权
    Method of reducing substrate coupling for chip inductors by creation of dielectric islands by selective EPI deposition 有权
    通过选择性EPI沉积形成介质岛来减少芯片电感器的衬底耦合的方法

    公开(公告)号：US06486017B1

    公开(公告)日：2002-11-26

    申请号：US10161772

    申请日：2002-06-04

    申请人： Purakh Raj Verma ,  Sanford Chu ,  Johnny Chew ,  Sia Choon Beng

    发明人： Purakh Raj Verma ,  Sanford Chu ,  Johnny Chew ,  Sia Choon Beng

    IPC分类号： H01L218234

    CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L27/08

    摘要： A new method is provided for the creation of a horizontal spiral inductor over the surface of a silicon substrate. A first layer of dielectric is deposited over the surface of the substrate, this first layer of dielectric is patterned and etched creation islands of first dielectric material overlying the surface of the substrate, the islands of first dielectric material align with coils of a thereover to be created spiral inductor. The openings created in the layer of dielectric by the patterning and etching of the first layer of dielectric are filled by selective deposition of epitaxial silicon therein. Second and third layers of dielectric are successively deposited over the surface of the first layer of dielectric. A spiral horizontal inductor is then created over the surface of the third layer of dielectric.

    摘要翻译： 提供了一种新的方法，用于在硅衬底的表面上创建水平螺旋电感器。 电介质的第一层沉积在衬底的表面上，该第一层电介质被图案化并且蚀刻产生覆盖衬底表面的第一介电材料的岛，第一介电材料的岛与其上的线圈对准， 创建螺旋电感。 通过第一层电介质的图案化和蚀刻在电介质层中产生的开口通过在其中选择性沉积外延硅来填充。 第二和第三层电介质依次沉积在第一层电介质的表面上。 然后在第三层电介质的表面上形成螺旋水平电感器。

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    2.
    发明申请
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US20050009357A1

    公开(公告)日：2005-01-13

    申请号：US10909523

    申请日：2004-08-02

    申请人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    3.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US07250669B2

    公开(公告)日：2007-07-31

    申请号：US10909523

    申请日：2004-08-02

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L29/00

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    4.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 失效
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US06869884B2

    公开(公告)日：2005-03-22

    申请号：US10225828

    申请日：2002-08-22

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。