公开(公告)号：US08838878B2

公开(公告)日：2014-09-16

申请号：US12791767

申请日：2010-06-01

Applicant: Siamak Arya ,  Dongsheng Xing

Inventor： Siamak Arya ,  Dongsheng Xing

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203

Abstract: A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.

Abstract translation: 示出了操作用于控制NAND存储器芯片的编程的控制器的方法。 NAND存储器芯片具有多个块，每个块具有一定量的存储，其中每个块中的存储量是最小可擦除单元。 该方法包括在临时存储器中存储第一组多组数据，其中数据组中的每一组将被存储在NAND存储器芯片的块中。 每组数据都被索引到要存储的块中。 最后，在相同的编程操作中，与相同块相关联的数据组被编程到相同的块中。

公开(公告)号：US20110296276A1

公开(公告)日：2011-12-01

申请号：US12791774

申请日：2010-06-01

Applicant: Siamak Arya

Inventor： Siamak Arya

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/3715 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/6337

Abstract: An output buffer circuit for a non-volatile memory stores a plurality of data bits and a plurality of error correction check (“ECC”) bits associated with the plurality of data bits. The output buffer circuit comprises an error check circuit for receiving the plurality of data bits and the plurality of ECC bits to determine if the plurality of data bits need to be corrected. The error check circuit supplies the plurality of data bits as its output, and generates a correction signal. An error correction circuit receives the plurality of data hits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. The output buffer circuit further has three or more storage circuits with each storage circuit having an input/output port. A bus connects to each of the storage circuits and to each other and supplies data bits between each storage circuit and between the nonvolatile memory and the storage circuits, and supplies data bits as the output of the output buffer circuit. A switch circuit is associated with each storage circuit for receiving the plurality of data bits; or the plurality of corrected data bits, and supplies same to the input/output port of the associated storage circuit and stores same as storage bits in the storage circuit, and supplies the storage bits as output of the storage circuit.

Abstract translation: 用于非易失性存储器的输出缓冲器电路存储与多个数据位相关联的多个数据位和多个纠错校验（“ECC”）位。 输出缓冲器电路包括用于接收多个数据位和多个ECC位的错误检查电路，以确定是否需要校正多个数据位。 错误检查电路提供多个数据位作为其输出，并产生校正信号。 误差校正电路接收多个数据命中和多个ECC位，并响应于校正信号产生多个校正数据位。 输出缓冲电路还具有三个或更多个存储电路，每个存储电路具有输入/输出端口。 总线连接到每个存储电路和彼此之间，并且在每个存储电路之间以及非易失性存储器和存储电路之间提供数据位，并且提供数据位作为输出缓冲器电路的输出。 开关电路与每个存储电路相关联，用于接收多个数据位; 或多个校正数据位，并将其提供给相关联的存储电路的输入/输出端口，并将其存储在存储电路中，并将存储位作为存储电路的输出提供。

公开(公告)号：US20100312926A1

公开(公告)日：2010-12-09

申请号：US12477799

申请日：2009-06-03

Applicant: Siamak Arya ,  Fong-Long Lin ,  Thao Thach Tran

Inventor： Siamak Arya ,  Fong-Long Lin ,  Thao Thach Tran

IPC: G06F3/00 ,  H04B7/005

CPC classification number: H04M1/72527 ,  H04M1/2535

Abstract: A USB switching device can selectively connect between a removable card and a mobile wireless communication device and a computer. The removable card has a first port; the mobile wireless communicating device has a second port while the computer has a third port. The switching device comprises a first full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a second full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a third full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The input of the first switch is connected to the first port. The input of the second switch is connected to the second port. The input of the third switch is connected to the third port. The first output of the first switch is connected to the second output of the second switch. The second output of the first switch is connected to the first output of the third switch. Finally, the first output of the second switch is connected to the second output of the third switch.

Abstract translation: USB切换设备可以选择性地连接可移动卡与移动无线通信设备和计算机之间。 可拆卸卡具有第一端口; 移动无线通信设备具有第二端口，而计算机具有第三端口。 开关装置包括具有输入和第一输出和第二输出的第一全双工开关，以及用于将输入连接到第一输出和将输入连接到第二输出的选择端口。 开关装置还包括具有输入和第一输出和第二输出的第二全双工开关，以及用于将输入连接到第一输出和将输入连接到第二输出的选择端口。 开关装置还包括具有输入和第一输出和第二输出的第三全双工开关，以及用于将输入连接到第一输出和将输入连接到第二输出的选择端口。 第一开关的输入连接到第一端口。 第二开关的输入连接到第二端口。 第三开关的输入连接到第三端口。 第一开关的第一输出连接到第二开关的第二输出端。 第一开关的第二输出端连接到第三开关的第一输出端。 最后，第二开关的第一输出连接到第三开关的第二输出端。

公开(公告)号：US06360313B1

公开(公告)日：2002-03-19

申请号：US09657758

申请日：2000-09-08

Applicant: Howard G. Sachs ,  Siamak Arya

Inventor： Howard G. Sachs ,  Siamak Arya

IPC: G06F938

CPC classification number: G06F9/382 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3853 ,  G06F9/3885

Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Abstract translation: 如上所述的计算系统，其中各个指令可以通过处理管线并行执行，并且由不同管线并行执行的指令同时被提供给管道。 该系统包括存储用于存储要执行的任意数量的指令。 要执行的指令被标记有指示其应该被分派到的管道的管道识别标签。 管道识别标签被提供给控制交叉开关的系统，使得能够使用标签来控制开关并且将适当的指令同时提供给不同的管道。

公开(公告)号：US5881258A

公开(公告)日：1999-03-09

申请号：US829632

申请日：1997-03-31

Applicant: Siamak Arya

Inventor： Siamak Arya

IPC: G06F9/318 ,  G06F9/38 ,  G06F9/00

CPC classification number: G06F9/30174 ,  G06F9/3853

Abstract: A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture, efficiently executes old software code by providing the processor with a compatibility circuit which receives old software code instructions from a secondary memory, groups these instructions according the new instruction set architecture and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.

Abstract translation: 包括单独的指令和数据高速缓存并且根据新的指令集架构执行指令的处理器通过向处理器提供从辅助存储器接收旧的软件代码指令的兼容性电路来有效地执行旧的软件代码，这些指令根据 新的指令集架构，并将这些分组的指令提供给处理器的指令高速缓存。 在该处理器中，旧的指令软件代码符合作为新指令集的子集的旧指令集。

公开(公告)号：US20120117444A1

公开(公告)日：2012-05-10

申请号：US12941926

申请日：2010-11-08

Applicant: Siamak Arya

Inventor： Siamak Arya

IPC: H03M13/09 ,  G06F11/10 ,  H03M13/05

CPC classification number: G06F11/108 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7208 ,  H03M13/1515

Abstract: A method of storing a plurality of blocks of data in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from, wherein each block of data is the minimum amount of data that can be written to or read from the non-volatile memory device. The method includes generating one or more blocks of error checking data based upon the plurality of blocks of data; and storing the plurality of blocks of said data and the one or more blocks of error checking data in the plurality of distinct physical non-volatile memory devices, with a block of data in a different physical memory device. Further, the method links the address of the plurality of blocks of data and the one or more blocks of error checking data in a cyclical link so that any entry to one of the blocks will result in a link all of the other blocks. The present invention also comprises a memory controller having a processor and a non-volatile memory for storing programming code that can perform the foregoing method. Finally, the present invention is a memory system that has a plurality of NAND memory devices device that can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The memory system further has a memory controller that has a processor and non-volatile memory for storing programming code that can be executed by the processor in accordance with the foregoing described method.

Abstract translation: 一种在多个物理上不同的非易失性存储器件中存储多个数据块的方法，每个独立的非易失性存储器件被独立地写入或读取，其中每个数据块是可写入或读取的最小数据量 非易失性存储器件。 该方法包括基于多个数据块生成一个或多个错误检查数据块; 以及将多个所述数据块和所述一个或多个错误校验数据块存储在所述多个不同物理非易失性存储器件中，并将数据块与不同的物理存储器件中的数据块进行存储。 此外，该方法将多个数据块的地址和一个或多个错误检查数据块链接在循环链路中，使得到块中的一个的任何条目将导致所有其他块的链接。 本发明还包括具有处理器和非易失性存储器的存储器控​​制器，用于存储可执行上述方法的程序代码。 最后，本发明是一种存储器系统，其具有多个NAND存储器件器件，其可以独立地写入数据块或从数据块中读取，其中块作为要写入或读取的最小存储单元。 存储器系统还具有存储器控制器，其具有处理器和非易失性存储器，用于存储可以由处理器根据前述描述的方法执行的编程代码。

公开(公告)号：US20090157946A1

公开(公告)日：2009-06-18

申请号：US11954577

申请日：2007-12-12

Applicant: Siamak Arya

Inventor： Siamak Arya

IPC: G06F12/06 ,  G06F13/28

CPC classification number: G06F13/4239

Abstract: In the present invention, a memory, and in particular, a NOR emulating memory comprises a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller. The controller has a first bus for receiving address signals from a host device and a second bus for interfacing with a RAM memory, and a third bus for interfacing with a NAND memory. A volatile RAM memory is connected to the second bus. A NAND memory is connected to the third bus. The controller receives commands and a first address from the first bus, and maps the first address to a second address in the NAND memory, and operates the NAND memory in response thereto. The RAM memory serves as cache for data to or from the NAND memory. The controller also maintains data coherence between the data stored in the RAM memory as cache and the data in the NAND memory. The invention further has a first buffer for storing data from the NAND memory in response to a read command to be written to the RAM memory, and a second buffer for storing data from the RAM memory to be written to the NAND memory. In the event of a read operation, if the data from the specified address is in the RAM memory, then the data is read from the RAM memory completing the read operation. In the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is sufficient space in the RAM memory to store an entire page of data from the NAND memory, then the entire page is read from the NAND memory, stored in the first buffer and then stored in the RAM memory, and from the specified address is read out, completing the read operation. Finally, in the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is insufficient space in the RAM memory to store an entire page of data from the NAND memory, then an entire page from the RAM memory is first stored in the second buffer, then an entire page is read from the NAND memory, stored in the first buffer, and from the first buffer, stored in the now freed RAM memory and data from the specified address is read out, completing the read operation. The page of data from the second buffer is subsequently stored back into the NAND memory after the completion of the read operation thereby reducing read latency.

公开(公告)号：US06892293B2

公开(公告)日：2005-05-10

申请号：US09057861

申请日：1998-04-09

Applicant: Howard G. Sachs ,  Siamak Arya

Inventor： Howard G. Sachs ,  Siamak Arya

IPC: G06F9/38

CPC classification number: G06F9/382 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3853 ,  G06F9/3885

Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Abstract translation: 如上所述的计算系统，其中各个指令可以通过处理管线并行执行，并且由不同管线并行执行的指令同时被提供给管道。 该系统包括存储用于存储要执行的任意数量的指令。 要执行的指令被标记有指示其应该被分派到的管道的管道识别标签。 管道识别标签被提供给控制交叉开关的系统，使得能够使用标签来控制开关并且将适当的指令同时提供给不同的管道。

公开(公告)号：US6047368A

公开(公告)日：2000-04-04

申请号：US828248

申请日：1997-03-31

Applicant: Siamak Arya

Inventor： Siamak Arya

IPC: G06F15/00

CPC classification number: G06F9/30174 ,  G06F9/382 ,  G06F9/3853

Abstract: A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture efficiently executes software code by providing the processor with a grouper circuit which receives software code instructions from a secondary memory and groups these instructions based upon the content of the instructions and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set. Such a system also functions where the processor maps instructions to itself

Abstract translation: 包括单独指令和数据高速缓存并且根据新指令集架构执行指令的处理器通过向处理器提供从二次存储器接收软件代码指令的分组器电路来有效地执行软件代码，并且基于第 指令并将这些分组的指令提供给处理器的指令高速缓存。 在该处理器中，旧指令软件代码符合作为新指令集的子集的旧指令集。 这样的系统还可以在处理器将指令映射到其自身的地方起作用

公开(公告)号：US08726130B2

公开(公告)日：2014-05-13

申请号：US12791774

申请日：2010-06-01

Applicant: Siamak Arya

Inventor： Siamak Arya

IPC: G11C29/00 ,  G11C16/04

CPC classification number: H03M13/3715 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/6337

Abstract: An output buffer circuit for a non-volatile memory comprises an error check circuit, an error correction circuit, a switch circuit, and three storage circuits. The error check circuit receives the plurality of data bits and the plurality of ECC bits from the non-volatile memory to determine if the plurality of data bits need to be corrected and generates a correction signal. The error correction circuit receives the plurality of data bits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. A switch enables the output buffer circuit to concurrently performs operations of error check, error correction, and transfer of data bits out of the output buffer circuit on three distinct pluralities of data bits. The switch allows reallocation of storage circuits to different operations without any data transfer.

Abstract translation: 用于非易失性存储器的输出缓冲电路包括错误校验电路，纠错电路，开关电路和三个存储电路。 错误检查电路从非易失性存储器接收多个数据位和多个ECC位，以确定是否需要校正多个数据位并产生校正信号。 误差校正电路接收多个数据位和多个ECC位，并响应于该校正信号产生多个校正数据位。 开关使得输出缓冲器电路能够在三个不同的多个数据位上同时执行错误检查，纠错和数据位从输出缓冲器电路传输的操作。 该开关允许将存储电路重新分配到不同的操作，而无需任何数据传输。