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公开(公告)号：US20180349099A1
公开(公告)日：2018-12-06
申请号：US15997955
申请日：2018-06-05
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： A method for optimal arrangement of a random generator on an electronic component, which includes a programmable integrated circuit and a basic structure consisting of a plurality of basic blocks, wherein during an initialization phase, starting from a starting configuration for a respective current arrangement of the random generator, the following are performed with a predefined number of repetitions, i.e., a predefined test sequence is performed for the current arrangement of the random generator, a test result is forwarded to a reconfiguration module and the current arrangement on the electronic component is reconfigured via the reconfiguration module, where upon each repetition, the test result of the current arrangement of the random generator is compared with the test result of a previous arrangement, and the current arrangement is saved in the reconfiguration module, if the test result for the current arrangement has a better test result than the previous arrangement.
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公开(公告)号：US11550881B2
公开(公告)日：2023-01-10
申请号：US17273761
申请日：2019-08-28
摘要： A method for managing licenses for soft IP on a partially reconfigurable hardware system, in particular an FPGA, wherein a license manager is provided in the non-configurable part of the hardware system, or is accessible only for the non-configurable part of the hardware system, where the license manager has exclusive access to a non-volatile memory in which license data having a time restriction of the useful life of at least one soft IP is stored, where before activating a particular soft IP, the license manager checks whether the useful life has expired, where the license manager only releases use of the soft IP if the useful life has not yet expired, where the license data is changed using a key, which is stored in a non-volatile memory for license data, and where a new key is stored and the preceding key is deleted when the license data is changed.
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公开(公告)号：US10416738B2
公开(公告)日：2019-09-17
申请号：US15399416
申请日：2017-01-05
IPC分类号： G06F1/24 , H03K17/22 , G06F21/70 , H03K19/0175 , H03K19/0185 , H03K19/177
摘要： A method for adjusting a pull resistor on a contact terminal of an electronic module arranged on a printed circuit board, in particular an ASIC, after initiating a restart of the electronic module which, during a run-up process, moves the electronic module from a switched-off state into a switched-on state, wherein after initiating a restart during the run-up process from a partial circuit arranged on the electronic module and operationally ready during the run-up process, adjustment information relating to a desired adjustment of the pull resistor is retrieved from a storage unit arranged on the printed circuit board outside of the electronic module and transmitted via a contact line between the electronic module and the storage unit, where the run-up process of the electronic module is only completed after successful adjustment of the respective pull resistor based on basis the retrieved adjustment information.
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公开(公告)号：US12058254B2
公开(公告)日：2024-08-06
申请号：US17271700
申请日：2019-06-25
CPC分类号： H04L9/0894 , G06F21/76
摘要： A method for storing key data in an electronic component formed as an integrated programmable circuit, such as a field programmable gate array, which includes a base structure consisting of base elements, wherein configuration data is loaded, for each current program, onto the base elements and stored in a volatile matter, the key data is divided into key sub-data blocks, and a base element position is selected for each key sub-data block, where upon generating the configuration data for each current program or circuit function of the electronic component, selected base element positions of the key sub-data blocks are considered, while loading the configuration data, key sub-data blocks are stored in the base elements defined by selected base element positions, and after successfully programming the electronic component, the key sub-data blocks of base elements specified by selected base element positions are ascertained and assembled to form the key data.
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公开(公告)号：US11704561B2
公开(公告)日：2023-07-18
申请号：US16955356
申请日：2018-12-12
IPC分类号： G06F30/323 , G06F30/327 , G06N3/08 , G06N3/063
CPC分类号： G06N3/08 , G06F30/323 , G06F30/327 , G06N3/063
摘要： A method for realizing an artificial neural network via an electronic integrated circuit (FPGA), wherein artificial neurons grouped into different interlinked layers for the artificial neural network, where a functional description is created for each neuron of the artificial neural network, taking into account a specifiable starting weighting, a synthesis is performed for each neuron based on the associated functional description with the associated specified starting weighting, a network list is determined as the synthesis result, in which at least a base element and a starting configuration belonging to the base element are stored for each neuron, a base element is formed as a lookup table (LUT) unit and an associated dynamic configuration cell, in which a current configuration for the LUT unit or the base element is stored, and where the network list is implemented as a starting configuration of the artificial neural network in the electronic integrated circuit.
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公开(公告)号：US11525858B2
公开(公告)日：2022-12-13
申请号：US16632083
申请日：2018-07-18
发明人： Friedrich Eppensteiner , Majid Ghameshlu , Martin Matschnig , Bernhard Fischer , Thomas Hinterstoisser , Herbert Taucher
摘要： A system and method for the predictive maintenance of electronic components that includes sensors at at least one position via which present values of system parameters, such as temperature and voltage, and a signal propagation time at the at least one position are determined, where values of the system parameters and the signal propagation time presently determined by the sensors are retrieved by a central monitoring unit, an individual valid limit value is determined for the signal propagation time at each of the at least one position via the central monitoring unit based on the presently determined values of the system parameters, and the presently determined signal propagation time at each of the at least one position is compared with the associated valid limit value, and a notification is sent to a superordinate level, if the signal propagation time exceeds the limit value to trigger replacement of the electronic component.
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公开(公告)号：US10146937B2
公开(公告)日：2018-12-04
申请号：US15248370
申请日：2016-08-26
摘要： A method for a logic circuit including a plurality of components and channels which are each assigned functional properties in a circuit model to simulate how the logic circuit functions, where the circuit model, in a section of the method, is expanded by mechanisms for security analysis, and where in a further section of the method, the following method steps are implemented via a simulation unit, i.e., check whether the security property of the respective component and/or the respective channel corresponds to the security requirement of the security-relevant data and generate a security risk report if it does not correspond thereto, apply a modeled attack to a component and/or to a channel, and determine a vulnerability of the security property of the respective component and/or of the respective channel to the applied attack, and if there is vulnerability of the security property, generate an attack report.
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