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    Physically unclonable function with precharge through bit lines
    1.
    发明授权
    Physically unclonable function with precharge through bit lines 有权

    公开(公告)号：US11539536B2

    公开(公告)日：2022-12-27

    申请号：US16850606

    申请日：2020-04-16

    Applicant: Silicon Laboratories Inc.

    Inventor： Jeffrey L. Sonntag ,  Hatem M. Osman ,  Gang Yuan

    IPC: H04L9/32 ,  G11C7/12 ,  G11C7/10 ,  H03M1/66 ,  G11C11/412 ,  G11C5/14 ,  G11C11/419

    Abstract: A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.

    Pre-Charge Technique For A Voltage Regulator
    2.
    发明申请
    Pre-Charge Technique For A Voltage Regulator 有权
    电压调节器的预充电技术

    公开(公告)号：US20160370816A1

    公开(公告)日：2016-12-22

    申请号：US14740386

    申请日：2015-06-16

    Applicant: Silicon Laboratories Inc.

    Inventor： Dazhi Wei ,  Gang Yuan ,  Erik Pankratz ,  Imranul Islam ,  Praveen Kallam ,  Axel Thomsen ,  Kenneth Wilson Fernald ,  Jinwen Xiao

    IPC: G05F1/575

    CPC classification number: G05F1/575 ,  G05F1/56 ,  H02M3/1588 ,  Y02B70/1466

    Abstract: In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.

    Abstract translation: 在一个实施例中，一种装置包括用于控制电压调节器的控制器。 控制器可以具有第一比较器电路，以将第一参考电压与反馈电压进行比较。 反过来，第一比较器电路可以包括：第一比较器，具有用于接收反馈电压的第一输入端子和用于接收参考电压的第二输入端子和输出节点，以基于该比较来输出误差信号; 以及耦合在所述第一输入端子和所述输出节点之间的第一预充电电路，被配置为将补偿网络的第一部分预先充电到预充电电平。 第一控制器还可以包括耦合到第一比较器电路的第二比较器电路，将误差信号与斜坡信号进行比较，并产生第一控制输出，以在第一操作模式下控制电压调节器的传动系。

    PHYSICALLY UNCLONABLE FUNCTION WITH PRECHARGE THROUGH BIT LINES
    3.
    发明申请
    PHYSICALLY UNCLONABLE FUNCTION WITH PRECHARGE THROUGH BIT LINES 有权

    公开(公告)号：US20210328817A1

    公开(公告)日：2021-10-21

    申请号：US16850606

    申请日：2020-04-16

    Applicant: Silicon Laboratories Inc.

    Inventor： Jeffrey L. Sonntag ,  Hatem M. Osman ,  Gang Yuan

    IPC: H04L9/32 ,  G11C7/12 ,  G11C7/10 ,  G11C11/419 ,  G11C11/412 ,  G11C5/14 ,  H03M1/66

    Abstract: A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.

    ADAPTIVE REFRESH RATE GENERATOR
    4.
    发明申请
    ADAPTIVE REFRESH RATE GENERATOR 有权

    公开(公告)号：US20250006245A1

    公开(公告)日：2025-01-02

    申请号：US18343007

    申请日：2023-06-28

    Applicant: Silicon Laboratories Inc.

    Inventor： Gang Yuan ,  Bertrand Jeffery Williams

    IPC: G11C11/4074 ,  G11C11/406 ,  G11C11/4099

    Abstract: In one embodiment, an apparatus includes: a replica sampler circuit to sample a first voltage that is based on a reference voltage, the replica sampler circuit to at least approximate a non-linearity of a bias generator. The replica sampler circuit may include: a switch circuit, when enabled, to pass the first voltage; and a capacitor coupled to the switch circuit, the capacitor to be charged by the first voltage. The apparatus also may include a comparator coupled to the replica sampler circuit, the comparator having a first input terminal to receive the sampled first voltage and a second input terminal to receive the reference voltage, where the comparator is to output a first signal having a first value when the sampled first voltage departs from the reference voltage by at least a threshold amount, to cause a refresh of at least a portion of the bias generator.

    NOISE-SHAPING CONVERTER WITH DIGITAL MODULATOR
    6.
    发明申请
    NOISE-SHAPING CONVERTER WITH DIGITAL MODULATOR 有权

    公开(公告)号：US20250080134A1

    公开(公告)日：2025-03-06

    申请号：US18454111

    申请日：2023-08-23

    Applicant: Silicon Laboratories Inc.

    Inventor： Gang Yuan

    IPC: H03M3/00 ,  H03M1/12 ,  H03M1/46

    Abstract: In one aspect, an apparatus includes: a first feedback digital-to-analog converter (DAC) to receive a first feedback signal from a first successive approximation register (SAR) and output a first analog signal; a comparator to compare the first analog signal with a reference voltage; the first SAR to store a digital value based on the comparison and provide the first feedback signal to the first DAC; a second feedback DAC to receive a modulated quantized residual error based on the comparison and output a second analog signal; a second SAR to store a quantized residual error; and a delta-sigma modulator (DSM) to modulate the quantized residual error and provide the modulated quantized residual error to the second feedback DAC.

    VOLTAGE GLITCH DETECTORS
    7.
    发明申请
    VOLTAGE GLITCH DETECTORS 有权

    公开(公告)号：US20250060409A1

    公开(公告)日：2025-02-20

    申请号：US18235156

    申请日：2023-08-17

    Applicant: Silicon Laboratories Inc.

    Inventor： Timothy Thomas Rueger ,  DeWitt Clinton Seward ,  Gang Yuan

    IPC: G01R31/30 ,  G01R19/165 ,  G01R31/40 ,  G06F21/75

    Abstract: Positive and negative glitch detectors detect glitches on a supply voltage node. The positive glitch detector has a capacitor and a resistor serially coupled between the supply voltage node and ground. An amplifier is coupled to a first node between the capacitor and resistor. A positive glitch results in the glitch on the first node (normally biased low) and generation of a clock pulse by the amplifier that causes a latch to assert its output to indicate the positive glitch. The negative glitch detector has a capacitor and resistor coupled in parallel between the supply voltage node and a second node. A negative glitch on the supply voltage node decreases the voltage on the second node (normally biased high) and an inverting amplifier coupled to the second node generates a clock pulse to cause a latch to assert its output to indicate the negative voltage glitch.

    Pre-charge technique for a voltage regulator
    10.
    发明授权
    Pre-charge technique for a voltage regulator 有权

    公开(公告)号：US09958888B2

    公开(公告)日：2018-05-01

    申请号：US14740386

    申请日：2015-06-16

    Applicant: Silicon Laboratories Inc.

    Inventor： Dazhi Wei ,  Gang Yuan ,  Erik Pankratz ,  Imranul Islam ,  Praveen Kallam ,  Axel Thomsen ,  Kenneth Wilson Fernald ,  Jinwen Xiao

    IPC: G05F1/575 ,  G05F1/56 ,  H02M3/158

    CPC classification number: G05F1/575 ,  G05F1/56 ,  H02M3/1588 ,  Y02B70/1466

    Abstract: In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.

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