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公开(公告)号:US11539536B2
公开(公告)日:2022-12-27
申请号:US16850606
申请日:2020-04-16
发明人: Jeffrey L. Sonntag , Hatem M. Osman , Gang Yuan
IPC分类号: H04L9/32 , G11C7/12 , G11C7/10 , H03M1/66 , G11C11/412 , G11C5/14 , G11C11/419
摘要: A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.
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公开(公告)号:US20160370816A1
公开(公告)日:2016-12-22
申请号:US14740386
申请日:2015-06-16
发明人: Dazhi Wei , Gang Yuan , Erik Pankratz , Imranul Islam , Praveen Kallam , Axel Thomsen , Kenneth Wilson Fernald , Jinwen Xiao
IPC分类号: G05F1/575
CPC分类号: G05F1/575 , G05F1/56 , H02M3/1588 , Y02B70/1466
摘要: In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.
摘要翻译: 在一个实施例中,一种装置包括用于控制电压调节器的控制器。 控制器可以具有第一比较器电路,以将第一参考电压与反馈电压进行比较。 反过来,第一比较器电路可以包括:第一比较器,具有用于接收反馈电压的第一输入端子和用于接收参考电压的第二输入端子和输出节点,以基于该比较来输出误差信号; 以及耦合在所述第一输入端子和所述输出节点之间的第一预充电电路,被配置为将补偿网络的第一部分预先充电到预充电电平。 第一控制器还可以包括耦合到第一比较器电路的第二比较器电路,将误差信号与斜坡信号进行比较,并产生第一控制输出,以在第一操作模式下控制电压调节器的传动系。
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公开(公告)号:US09680420B2
公开(公告)日:2017-06-13
申请号:US14869924
申请日:2015-09-29
发明人: Gang Yuan , Matthew Powell
CPC分类号: H03F1/26 , H03F1/083 , H03F1/086 , H03F3/3022 , H03F3/45179 , H03F3/45242 , H03F2200/408 , H03F2203/45116
摘要: An apparatus includes a multi-stage amplifier. The multi-stage amplifier includes first, second, and third amplifier circuits coupled in a cascade configuration. The multi-stage amplifier further includes first, second, and third compensation networks. The first compensation network is coupled between the output of the third amplifier circuit and the input of the second amplifier circuit. The second compensation network is coupled between the output of the third amplifier circuit and the input of the third amplifier circuit. The third compensation network is coupled between the output of the second amplifier circuit and the input of the second amplifier circuit.
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公开(公告)号:US20170093342A1
公开(公告)日:2017-03-30
申请号:US14869924
申请日:2015-09-29
发明人: Gang Yuan , Matthew Powell
CPC分类号: H03F1/26 , H03F1/083 , H03F1/086 , H03F3/3022 , H03F3/45179 , H03F3/45242 , H03F2200/408 , H03F2203/45116
摘要: An apparatus includes a multi-stage amplifier. The multi-stage amplifier includes first, second, and third amplifier circuits coupled in a cascade configuration. The multi-stage amplifier further includes first, second, and third compensation networks. The first compensation network is coupled between the output of the third amplifier circuit and the input of the second amplifier circuit. The second compensation network is coupled between the output of the third amplifier circuit and the input of the third amplifier circuit. The third compensation network is coupled between the output of the second amplifier circuit and the input of the second amplifier circuit.
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公开(公告)号:US20210328817A1
公开(公告)日:2021-10-21
申请号:US16850606
申请日:2020-04-16
发明人: Jeffrey L. Sonntag , Hatem M. Osman , Gang Yuan
IPC分类号: H04L9/32 , G11C7/12 , G11C7/10 , G11C11/419 , G11C11/412 , G11C5/14 , H03M1/66
摘要: A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.
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公开(公告)号:US20170155386A1
公开(公告)日:2017-06-01
申请号:US14955008
申请日:2015-11-30
发明人: Gang Yuan , Shouli Yan , Matthew Powell
IPC分类号: H03K17/687 , H03F3/45 , H03F1/02
CPC分类号: H03K17/687 , H03F1/0205 , H03F3/45179 , H03F3/45278 , H03F3/45726 , H03F3/45892 , H03F2203/45038 , H03F2203/45212 , H03F2203/45696 , H03F2203/45726
摘要: An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.
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公开(公告)号:US09958888B2
公开(公告)日:2018-05-01
申请号:US14740386
申请日:2015-06-16
发明人: Dazhi Wei , Gang Yuan , Erik Pankratz , Imranul Islam , Praveen Kallam , Axel Thomsen , Kenneth Wilson Fernald , Jinwen Xiao
CPC分类号: G05F1/575 , G05F1/56 , H02M3/1588 , Y02B70/1466
摘要: In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.
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公开(公告)号:US09742397B2
公开(公告)日:2017-08-22
申请号:US14955008
申请日:2015-11-30
发明人: Gang Yuan , Shouli Yan , Matthew Powell
IPC分类号: H03F1/02 , H03K17/687 , H03F3/45
CPC分类号: H03K17/687 , H03F1/0205 , H03F3/45179 , H03F3/45278 , H03F3/45726 , H03F3/45892 , H03F2203/45038 , H03F2203/45212 , H03F2203/45696 , H03F2203/45726
摘要: An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.
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