公开(公告)号：US20170255467A1

公开(公告)日：2017-09-07

申请号：US15061018

申请日：2016-03-04

Applicant: Silicon Laboratories Inc.

Inventor： Mark W. Johnson ,  Paul Zavalney ,  Marius Grannæs ,  Oeivind A. G. Loe

IPC: G06F9/30

CPC classification number: G06F9/30047 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/3806 ,  G06F9/381 ,  G06F12/0875 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/452 ,  Y02D10/13

Abstract: An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.

公开(公告)号：US10180839B2

公开(公告)日：2019-01-15

申请号：US15061018

申请日：2016-03-04

Applicant: Silicon Laboratories Inc.

Inventor： Mark W. Johnson ,  Paul Zavalney ,  Marius Grannæs ,  Oeivind A. G. Loe

IPC: G06F9/40 ,  G06F12/12 ,  G06F9/30 ,  G06F9/32 ,  G06F12/0875 ,  G06F9/38 ,  G06F12/121

Abstract: An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.