公开(公告)号：US09564915B1

公开(公告)日：2017-02-07

申请号：US15061039

申请日：2016-03-04

Applicant: Silicon Laboratories Inc.

Inventor： Wajid Hassan Minhass ,  Oeivind A. G. Loe

IPC: H03M1/12 ,  H03M1/00

CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/0624

Abstract: An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in response to a trigger signal. The ADC core circuit further provide the digital signal as an output of the ADC. The ADC further includes internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period has expired.

Abstract translation: 集成电路（IC）包括模数转换器（ADC）。 ADC包括集成在IC中的ADC内核电路，用于接收模拟信号，以根据触发信号将模拟信号转换为数字信号。 ADC内核电路进一步提供数字信号作为ADC的输出。 ADC还包括集成在ADC中的内部触发电路，以在规定的延迟时间到期后向ADC提供触发信号。

公开(公告)号：US10180839B2

公开(公告)日：2019-01-15

申请号：US15061018

申请日：2016-03-04

Applicant: Silicon Laboratories Inc.

Inventor： Mark W. Johnson ,  Paul Zavalney ,  Marius Grannæs ,  Oeivind A. G. Loe

IPC: G06F9/40 ,  G06F12/12 ,  G06F9/30 ,  G06F9/32 ,  G06F12/0875 ,  G06F9/38 ,  G06F12/121

Abstract: An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.

公开(公告)号：US10020815B2

公开(公告)日：2018-07-10

申请号：US15427014

申请日：2017-02-07

Applicant: Silicon Laboratories Inc.

Inventor： Wajid Hassan Minhass ,  Oeivind A. G. Loe

IPC: H03M1/12 ,  H03M1/00

CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/0624

Abstract: An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in response to a trigger signal. The ADC core circuit further provide the digital signal as an output of the ADC. The ADC further includes internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period has expired.

公开(公告)号：US20170257109A1

公开(公告)日：2017-09-07

申请号：US15427014

申请日：2017-02-07

Applicant: Silicon Laboratories Inc.

Inventor： Wajid Hassan Minhass ,  Oeivind A. G. Loe

IPC: H03M1/12 ,  H03M1/00

CPC classification number: H03M1/12 ,  H03M1/002 ,  H03M1/0624

Abstract: An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in response to a trigger signal. The ADC core circuit further provide the digital signal as an output of the ADC. The ADC further includes internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period has expired.

公开(公告)号：US20170255467A1

公开(公告)日：2017-09-07

申请号：US15061018

申请日：2016-03-04

Applicant: Silicon Laboratories Inc.

Inventor： Mark W. Johnson ,  Paul Zavalney ,  Marius Grannæs ,  Oeivind A. G. Loe

IPC: G06F9/30

CPC classification number: G06F9/30047 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/3806 ,  G06F9/381 ,  G06F12/0875 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/452 ,  Y02D10/13

Abstract: An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.