公开(公告)号：US12045645B2

公开(公告)日：2024-07-23

申请号：US16945871

申请日：2020-08-02

申请人： Silicon Laboratories Inc.

发明人： Subba Reddy Kallam ,  Partha Sarathy Murali ,  Venkat Mattela ,  Venkata Siva Prasad Pulagam

IPC分类号： G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  H04L49/90 ,  H04L65/60 ,  H04W4/80 ,  H04W12/06 ,  H04W80/02 ,  H04W80/04

CPC分类号： G06F9/4812 ,  G06F9/30101 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/5061 ,  H04L49/90 ,  H04L65/60 ,  H04W4/80 ,  H04W12/06 ,  H04W80/02 ,  H04W80/04

摘要： A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.

公开(公告)号：US10817200B2

公开(公告)日：2020-10-27

申请号：US15794008

申请日：2017-10-26

申请人： Silicon Laboratories Inc.

发明人： Partha Sarathy Murali ,  Venkata Siva Prasad Pulagam ,  Sailaja Dharani Naga Sankabathula ,  Venkat Rao Gunturu ,  Subba Reddy Kallam

IPC分类号： G06F3/06 ,  G06F13/40

摘要： A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.

公开(公告)号：US12101658B2

公开(公告)日：2024-09-24

申请号：US16945870

申请日：2020-08-02

申请人： Silicon Laboratories Inc.

发明人： Subba Reddy Kallam ,  Partha Murali ,  Venkat Mattela ,  Venkata Siva Prasad Pulagam

IPC分类号： H04W28/02 ,  G06F9/30 ,  G06F9/38 ,  H04W4/80 ,  H04W16/18 ,  H04W72/54 ,  H04W72/563 ,  H04W84/12

CPC分类号： H04W28/0231 ,  G06F9/30098 ,  G06F9/3836 ,  H04W4/80 ,  H04W16/18 ,  H04W72/54 ,  H04W72/563 ,  H04W84/12

摘要： A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.