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1.发明申请公开(公告)号：US20190235789A1
公开(公告)日：2019-08-01
申请号：US16012782
申请日：2018-06-20
Applicant: Silicon Motion Inc.
Inventor： Wei-Lun Yan , Ming-Yen Lin , Chin-Pang Chang
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/064 , G06F3/0656 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10
Abstract: A method for performing writing management in a memory device, the memory device, and the controller thereof are provided. The method may include: writing first partial data of even-page data into a non-volatile (NV) memory; transmitting a first set of commands without a confirmation command to the NV memory, to write the first partial data and second partial data of the even-page data into an internal buffer within the NV memory; transmitting a second set of commands and the confirmation command to the NV memory, to write the first partial data and the second partial data into a block of the NV memory; writing third partial data of odd-page data into the NV memory; and writing the first and the second partial data into an even page of another block of the NV memory, and writing the third and fourth partial data into an odd page of this block.
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公开(公告)号：US10437520B2
公开(公告)日：2019-10-08
申请号：US16012782
申请日：2018-06-20
Applicant: Silicon Motion Inc.
Inventor： Wei-Lun Yan , Ming-Yen Lin , Chin-Pang Chang
Abstract: A method for performing writing management in a memory device, the memory device, and the controller thereof are provided. The method may include: writing first partial data of even-page data into a non-volatile (NV) memory; transmitting a first set of commands without a confirmation command to the NV memory, to write the first partial data and second partial data of the even-page data into an internal buffer within the NV memory; transmitting a second set of commands and the confirmation command to the NV memory, to write the first partial data and the second partial data into a block of the NV memory; writing third partial data of odd-page data into the NV memory; and writing the first and the second partial data into an even page of another block of the NV memory, and writing the third and fourth partial data into an odd page of this block.
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公开(公告)号：US20190079673A1
公开(公告)日：2019-03-14
申请号：US16190994
申请日：2018-11-14
Applicant: Silicon Motion, Inc.
Inventor： Chin-Pang Chang , Chun-Yi Lo
CPC classification number: G06F3/061 , G06F1/04 , G06F1/08 , G06F1/12 , G06F3/0653 , G06F3/0679 , G06F12/0246 , G06F2212/7208
Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
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公开(公告)号：US20150160688A1
公开(公告)日：2015-06-11
申请号：US14504014
申请日：2014-10-01
Applicant: Silicon Motion, Inc.
Inventor： Chin-Pang Chang , Chun-Yi Lo
CPC classification number: G06F3/061 , G06F1/04 , G06F1/08 , G06F1/12 , G06F3/0653 , G06F3/0679 , G06F12/0246 , G06F2212/7208
Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
Abstract translation: 一种包括闪存和控制器的数据存储设备。 控制器使得闪存能够根据时钟信号的第一预定触发沿发送存储在闪速存储器中的预定参数，并且根据时钟信号的第一预定触发沿读出由闪存发送的预定参数，以获得 异步模式下的第一个参考参数。 控制器使闪存切换到同步模式并发送预定参数，并根据时钟信号的第一预定触发沿读取闪存发送的预定参数，以便在检测模式下获得第二参考参数。
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公开(公告)号：US10802720B2
公开(公告)日：2020-10-13
申请号：US16190994
申请日：2018-11-14
Applicant: Silicon Motion, Inc.
Inventor： Chin-Pang Chang , Chun-Yi Lo
Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
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Patent Agency Ranking
公开(公告)号：US10754585B2
公开(公告)日：2020-08-25
申请号：US16547594
申请日：2019-08-22
Applicant: Silicon Motion Inc.
Inventor： Wei-Lun Yan , Ming-Yen Lin , Chin-Pang Chang
Abstract: A method for performing writing management in a memory device, the memory device, and the controller thereof are provided. The method may include: writing first partial data of even-page data into a non-volatile (NV) memory; transmitting a first set of commands without a confirmation command to the NV memory, to write the first partial data and second partial data of the even-page data into an internal buffer within the NV memory; transmitting a second set of commands and the confirmation command to the NV memory, to write the first partial data and the second partial data into a block of the NV memory; writing third partial data of odd-page data into the NV memory; and writing the first and the second partial data into an even page of another block of the NV memory, and writing the third and fourth partial data into an odd page of this block.
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7.发明申请公开(公告)号：US20190377517A1
公开(公告)日：2019-12-12
申请号：US16547594
申请日：2019-08-22
Applicant: Silicon Motion Inc.
Inventor： Wei-Lun Yan , Ming-Yen Lin , Chin-Pang Chang
Abstract: A method for performing writing management in a memory device, the memory device, and the controller thereof are provided. The method may include: writing first partial data of even-page data into a non-volatile (NV) memory; transmitting a first set of commands without a confirmation command to the NV memory, to write the first partial data and second partial data of the even-page data into an internal buffer within the NV memory; transmitting a second set of commands and the confirmation command to the NV memory, to write the first partial data and the second partial data into a block of the NV memory; writing third partial data of odd-page data into the NV memory; and writing the first and the second partial data into an even page of another block of the NV memory, and writing the third and fourth partial data into an odd page of this block.
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公开(公告)号：US10162532B2
公开(公告)日：2018-12-25
申请号：US15434927
申请日：2017-02-16
Applicant: Silicon Motion, Inc.
Inventor： Chin-Pang Chang , Chun-Yi Lo
Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
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公开(公告)号：US20170160938A1
公开(公告)日：2017-06-08
申请号：US15434927
申请日：2017-02-16
Applicant: Silicon Motion, Inc.
Inventor： Chin-Pang Chang , Chun-Yi Lo
CPC classification number: G06F3/061 , G06F1/04 , G06F1/08 , G06F1/12 , G06F3/0653 , G06F3/0679 , G06F12/0246 , G06F2212/7208
Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
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公开(公告)号：US09612610B2
公开(公告)日：2017-04-04
申请号：US14504014
申请日：2014-10-01
Applicant: Silicon Motion, Inc.
Inventor： Chin-Pang Chang , Chun-Yi Lo
CPC classification number: G06F3/061 , G06F1/04 , G06F1/08 , G06F1/12 , G06F3/0653 , G06F3/0679 , G06F12/0246 , G06F2212/7208
Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
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