Method for performing power saving control in a memory device, associated memory device and memory controller thereof, and associated electronic device

    公开(公告)号:US10936046B2

    公开(公告)日:2021-03-02

    申请号:US16273166

    申请日:2019-02-12

    Abstract: A method for performing power saving control in memory device, the associated memory device and memory controller thereof, and the associated electronic device are provided, where the method is applicable to the memory controller, and the memory device includes the memory controller and a non-volatile (NV) memory. The method may include: during transmitting to a host device, sending end of burst (EOB)-related symbols to the host device, in order to notify the host device of EOB; controlling a physical layer (PHY) circuit to turn off a clock source within the PHY circuit, in order to save power, wherein the PHY circuit is positioned in a transmission interface circuit within the memory controller, and the transmission interface circuit is arranged to perform communications with the host device for the memory device; and when receiving a trigger signal from the host device, utilizing the PHY circuit to turn on the clock source.

    Controller circuit and method for estimating transmission delay

    公开(公告)号:US10248608B2

    公开(公告)日:2019-04-02

    申请号:US15837072

    申请日:2017-12-11

    Abstract: A controller circuit includes a first signal processing device processing signals in accordance with a first predetermined rule, a second signal processing device processing signals in accordance with a second predetermined rule, a data bus coupled between the first signal processing device and the second signal processing device and comprising multiple data lines, and a confirm signal line coupled between the first signal processing device and the second signal processing device. The first signal processing device transmits a synchronization signal to the second signal processing device via the data bus. The second signal processing device estimates transmission delay on each data line according to the synchronization signal, performs transmission delay compensation on each data line according to the estimated transmission delay and transmits a confirmation signal on the confirm signal line to notify the first signal processing device that the transmission delay compensation is complete.

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